Add initial support for SMSC SIO1007 SuperI/O chip
early_serial and some ACPI needed for compilation Change-Id: I5dd970676488697156e0630392884f31149ac85b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/824 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
8198600b0b
commit
6626d6a9e3
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@ -36,6 +36,8 @@ config SUPERIO_SMSC_LPC47N227
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bool
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config SUPERIO_SMSC_SIO10N268
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bool
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config SUPERIO_SMSC_SIO1007
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bool
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config SUPERIO_SMSC_KBC1100
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bool
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config SUPERIO_SMSC_SMSCSUPERIO
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@ -27,6 +27,7 @@ subdirs-y += lpc47m15x
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subdirs-y += lpc47n217
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subdirs-y += lpc47n227
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subdirs-y += sio10n268
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subdirs-y += sio1007
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subdirs-y += kbc1100
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subdirs-y += smscsuperio
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subdirs-y += sio1036
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@ -0,0 +1,299 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// Scope is \_SB.PCI0.LPCB
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Device (SIO) {
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Name (_ADR, 0x2E)
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OperationRegion (SIOA, SystemIO, 0x2E, 0x02)
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Field (SIOA, ByteAcc, NoLock, Preserve)
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{
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SI2E, 8,
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SI2F, 8,
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}
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IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve)
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{
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Offset (0x02),
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SCNT, 8, /* Configure Control */
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Offset (0x07),
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SLDN, 8, /* Logical Device Number */
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Offset (0x30),
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SACT, 8, /* Activate */
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Offset (0x60),
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IO0H, 8, /* Base Address 0 MSB */
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IO0L, 8, /* Base Address 0 LSB */
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Offset (0x62),
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IO1H, 8, /* Base Address 1 MSB */
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IO1L, 8, /* Base Address 1 LSB */
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Offset (0x70),
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IQ00, 8, /* Interrupt Select */
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}
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Name (SFDC, 0) /* Floppy Disk Controller */
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Name (SSP1, 1) /* Serial Port 1 */
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Name (SENV, 4) /* Environment Controller */
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Name (SKBC, 5) /* Keyboard */
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Name (SKBM, 6) /* Mouse */
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Name (SGPI, 7) /* GPIO */
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Name (SINF, 10) /* Consumer IR */
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Method (ENTR, 0, NotSerialized)
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{
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Store (0x87, SI2E)
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Store (0x01, SI2E)
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Store (0x55, SI2E)
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Store (0x55, SI2E)
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}
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Method (EXIT, 0, NotSerialized)
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{
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Store (0x02, SCNT)
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}
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/* Parse activate register for an LDN */
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Method (ISEN, 1, NotSerialized)
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{
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ENTR ()
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Store (Arg0, SLDN)
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Store (SACT, Local0)
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EXIT ()
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/* Check if it exists */
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If (LEqual (Local0, 0xFF))
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{
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Return (0x00)
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}
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/* Check if activated */
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If (LEqual (Local0, One))
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{
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Return (0x0F)
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}
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Else
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{
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Return (0x0D)
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}
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}
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/* Enable an LDN via the activate register */
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Method (SENA, 1, NotSerialized)
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{
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ENTR ()
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Store (Arg0, SLDN)
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Store (One, SACT)
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EXIT ()
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}
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/* Disable an LDN via the activate register */
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Method (SDIS, 1, NotSerialized)
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{
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ENTR ()
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Store (Arg0, SLDN)
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Store (Zero, SACT)
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EXIT ()
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}
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#ifdef SIO_ENABLE_ENVC
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Device (ENVC) {
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 10)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SENV))
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
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IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
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IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
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})
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OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07)
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Field (ECAP, ByteAcc, NoLock, Preserve)
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{
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Offset (0x05),
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ECAI, 8, // Address Index Register
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ECAD, 8, // Address Data Register
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}
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// Registers for thermal zone implementations
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IndexField (ECAI, ECAD, ByteAcc, NoLock, Preserve)
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{
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Offset (0x29),
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TIN1, 8, // TMPIN1 Reading
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TIN2, 8, // TMPIN2 Reading
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TIN3, 8, // TMPIN3 Reading
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Offset (0x6b),
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F2PS, 8, // FAN2 PWM Setting
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Offset (0x73),
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F3PS, 8, // FAN3 PWM Setting
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}
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}
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#endif
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#ifdef SIO_ENABLE_GPIO
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Device (GPIO) {
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 11)
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Method (_STA, 0, NotSerialized) {
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Return (0x0F)
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
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IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
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IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
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})
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}
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#endif
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#ifdef SIO_ENABLE_COM1
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Device (COM1) {
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Name (_HID, EISAID ("PNP0501"))
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Name (_UID, 1)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SSP1))
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
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IRQNoFlags () {4}
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
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IRQNoFlags () {4}
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})
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}
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#endif
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#ifdef SIO_ENABLE_PS2K
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Device (PS2K) // Keyboard
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{
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Name (_HID, EISAID("PNP0303"))
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Name (_CID, EISAID("PNP030B"))
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SKBC))
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}
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x60, 0x60, 0x01, 0x01)
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IO (Decode16, 0x64, 0x64, 0x01, 0x01)
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IRQNoFlags () {1}
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})
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Name (_PRS, ResourceTemplate()
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{
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IO (Decode16, 0x60, 0x60, 0x01, 0x01)
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IO (Decode16, 0x64, 0x64, 0x01, 0x01)
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IRQNoFlags () {1}
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})
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}
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#endif
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#ifdef SIO_ENABLE_PS2M
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Device (PS2M) // Mouse
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{
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Name (_HID, EISAID("PNP0F13"))
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SKBM))
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}
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Name (_CRS, ResourceTemplate()
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{
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IRQNoFlags () {12}
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})
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Name (_PRS, ResourceTemplate()
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{
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IRQNoFlags () {12}
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})
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}
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#endif
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#ifdef SIO_ENABLE_FDC0
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Device (FDC0) // Floppy controller
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{
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Name (_HID, EISAID ("PNP0700"))
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SFDC))
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}
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
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IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
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IRQNoFlags () {6}
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DMA (Compatibility, NotBusMaster, Transfer8) {2}
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})
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Name (_PRS, ResourceTemplate()
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{
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IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
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IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
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IRQNoFlags () {6}
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DMA (Compatibility, NotBusMaster, Transfer8) {2}
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})
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}
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#endif
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#ifdef SIO_ENABLE_INFR
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Device (INFR) // Infrared controller
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{
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Name (_HID, EISAID ("PNP0510"))
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SINF))
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}
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
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IRQNoFlags () { SIO_INFR_IRQ }
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})
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Name (_PRS, ResourceTemplate()
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{
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IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
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IRQNoFlags () { SIO_INFR_IRQ }
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})
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}
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#endif
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}
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@ -0,0 +1,64 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* The chip could be bootstrap mapped to one of four LPC addresses:
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* 0x2e, 0x4e, 0x162e, and 0x164e.
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*/
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const u16 sio1007_lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e};
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static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
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{
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u8 reg_value;
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outb(reg, lpc_port);
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reg_value = inb(lpc_port + 1);
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reg_value &= ~mask;
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reg_value |= (value & mask);
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outb(reg_value, lpc_port + 1);
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}
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static int sio1007_enable_uart_at(u16 port)
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{
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/* Enable config mode. */
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outb(0x55, port);
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if (inb(port) != 0x55)
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return 0; /* There is no LPC device at this address. */
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/* Registers 12 and 13 hold config address, look for a match. */
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outb(0x12, port);
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if (inb(port + 1) != (port & 0xff))
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return 0;
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outb(0x13, port);
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if (inb(port + 1) != (port >> 8))
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return 0;
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/* This must be the sio1007, enable the UART. */
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/* turn on power */
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sio1007_setreg(port, 0x2, 1 << 3, 1 << 3);
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/* enable high speed */
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sio1007_setreg(port, 0xc, 1 << 6, 1 << 6);
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/* set the base address */
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sio1007_setreg(port, 0x24, CONFIG_TTYS0_BASE >> 2, 0xff);
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/* Disable config mode. */
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outb(0xaa, port);
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return 1;
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}
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