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soc/intel/cnl: Add provision to configure SD controller write protect pin 

Cometlake FSP allows provison to configure SD controller WP pin, As
some of board design might choose not to use the SD WP pin from SD
card controller. This implementation adds a config that allows to
enable/disable SD controller WP pin configuration from FSP.

BUG=b:123907904

Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34900
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2019-08-16 11:56:40 +05:30 committed by Furquan Shaikh
parent c43001eb14
commit 662c61d449
2 changed files with 5 additions and 0 deletions
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2
src/soc/intel/cannonlake/chip.h
View File

@ -186,6 +186,8 @@ struct soc_intel_cannonlake_config {
uint8_t EmmcHs400RxStrobeDll1; uint8_t EmmcHs400RxStrobeDll1;
/* 0-78: number of active delay for TX data, unit is 125 psec */ /* 0-78: number of active delay for TX data, unit is 125 psec */
uint8_t EmmcHs400TxDataDll; uint8_t EmmcHs400TxDataDll;
/* Enable/disable SD card write protect pin configuration on CML */
uint8_t ScsSdCardWpPinEnabled;
/* Integrated Sensor */ /* Integrated Sensor */
uint8_t PchIshEnable; uint8_t PchIshEnable;

3
src/soc/intel/cannonlake/fsp_params.c
View File

@ -336,6 +336,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->ScsSdCardEnabled = dev->enabled; params->ScsSdCardEnabled = dev->enabled;
params->SdCardPowerEnableActiveHigh = params->SdCardPowerEnableActiveHigh =
CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
#if CONFIG(SOC_INTEL_COMETLAKE)
params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled;
#endif
} }
dev = pcidev_path_on_root(PCH_DEVFN_UFS); dev = pcidev_path_on_root(PCH_DEVFN_UFS);