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soc/intel/cannonlake: Add some missing DEVFN macros 

BUG=b:130217151

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If535ad0bdd46d3315493155e64968d305aa34799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55967
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-06-29 11:32:38 -06:00
parent 61005c8eb5
commit 664c58ab95
1 changed files with 12 additions and 0 deletions
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12
src/soc/intel/cannonlake/include/soc/pci_devs.h
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@ -22,6 +22,14 @@
#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
#endif
#define SA_DEV_SLOT_PEG 0x01
#define SA_DEVFN_PEG0 PCI_DEVFN(SA_DEV_SLOT_PEG, 0)
#define SA_DEVFN_PEG1 PCI_DEVFN(SA_DEV_SLOT_PEG, 1)
#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 2)
#define SA_DEV_PEG0 PCI_DEV(0, SA_DEV_SLOT_PEG, 0)
#define SA_DEV_PEG1 PCI_DEV(0, SA_DEV_SLOT_PEG, 1)
#define SA_DEV_PEG2 PCI_DEV(0, SA_DEV_SLOT_PEG, 2)
#define SA_DEV_SLOT_IGD 0x02
#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
@ -34,6 +42,10 @@
#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
#define SA_DEV_SLOT_GNA 0x08
#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0)
#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0)
/* PCH Devices */
#define PCH_DEV_SLOT_THERMAL 0x12
#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0)