nb/intel/sandybridge: Add ECC error injection register information
Change-Id: I669a611e804d67bb6e87775d273dc24b03b06691 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44396 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -188,6 +188,85 @@
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* [6] Cleared with a new sequence, and set when done and refresh counter is drained.
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* [6] Cleared with a new sequence, and set when done and refresh counter is drained.
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*/
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*/
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/*
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* ### ECC error injection registers ###
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*
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* ECC_INJECT_COUNT_ch(channel)
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* Defines the count of write chunks (64-bit data packets) until the
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* next ECC error injection. This only seems to apply if the ECC_inject
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* field in the ECC_DFT register is 110 or 111. The count is of chunks
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* in order to allow creating ECC errors on different 64-bit chunks.
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*
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* Note that this register is only 32-bit.
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*
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* ECC_DFT_ch(channel)
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* Control ECC DFT features, such as ECC4ANA, error inject, etc.
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*
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* Bitfields:
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* [7..0] 8-bit fill value for ECC4ANA function.
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* [9..8] ECC4ANA trigger:
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* 00: ECC4ANA is off, no trigger.
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* 10: Trigger on single-bit or uncorrectable error.
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* 11: Trigger on uncorrectable error.
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*
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* [10] ECC4ANA byte select:
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* 0: Byte 0
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* 1: Byte 7
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*
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* [13..11] ECC_inject: ECC error inject options:
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* 000: No ECC error injection.
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* 100: Inject non-recoverable ECC error on GODLAT indication.
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* 101: Inject non-recoverable ECC error on ECC_INJ_ADDR_COMPARE reg match.
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* 110: Reserved.
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* 111: Inject non-recoverable ECC error on ECC error insertion counter.
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*
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* [14] ECC correction disable: when set, the MC reports every error as uncorrectable.
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* [15] Mark incoming transactions for ECC4ANA based on ECC_INJ_ADDR_COMPARE reg match.
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*
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* SCHED_SECOND_CBIT
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* More chicken bits!
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*
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* Bitfields:
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*
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* [11] Disable ECC4ANA Bug Fix. WARNING: This register is only for Ivy Bridge!
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*
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* MAD_DIMM_ch(channel)
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* Channel characteristics: number of DIMMs, number of ranks, size,
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* (enhanced) interleave options and ECC options.
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*
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* Bitfields:
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* [7..0] DIMM A size in 256 MiB units.
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* [15..8] DIMM B size in 256 MiB units.
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* [16] Select which of the DIMMs is DIMM A, should be the larger DIMM.
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* [17] DIMM A number of ranks. (0 => Single Rank, 1 => Dual Rank)
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* [18] DIMM B number of ranks.
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* [19] DIMM A DDR chip width. (0 => x8, 1 => x16)
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* [20] DIMM B DDR chip width.
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* [21] Enable Rank Interleave.
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* [22] Enable Enhanced Rank Interleave.
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* [25..24] ECC control:
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* 00: No ECC.
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* 01: ECC is active in IO, ECC logic is not active. Used with IOSAV training.
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* 10: ECC is disabled in IO, but ECC logic is enabled. Used with ECC4ANA mode.
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* 11: ECC active in both IO and ECC logic.
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*
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* ECC_INJ_ADDR_COMPARE, ECC_INJ_ADDR_MASK
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*
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* Address compare for ECC error inject. Error injection is issued when
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* ECC_INJ_ADDR_COMPARE[31..0] = ADDR[37..6] & ECC_INJ_ADDR_MASK[31..0].
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*
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* MC_LOCK
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*
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* Locking of MC registers. Each bit locks one group of registers.
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*
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* Bitfields:
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* [0] Lock all the address map registers.
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* [1] Lock all the MC configuration registers including MCIO.
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* [2] Lock all IOSAV and Init registers.
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* [3] Lock all power management registers.
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* [7] Lock all DFT features.
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*/
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/* Indexed register helper macros */
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/* Indexed register helper macros */
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#define Gz(r, z) ((r) + ((z) << 8))
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#define Gz(r, z) ((r) + ((z) << 8))
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#define Ly(r, y) ((r) + ((y) << 2))
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#define Ly(r, y) ((r) + ((y) << 2))
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@ -401,6 +480,9 @@
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#define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */
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#define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */
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#define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */
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#define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */
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#define ECC_INJ_ADDR_COMPARE 0x5090 /* Address compare for ECC error inject */
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#define ECC_INJ_ADDR_MASK 0x5094 /* Address mask for ECC error inject */
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#define MC_LOCK 0x50fc /* Memory Controlller Lock register */
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#define MC_LOCK 0x50fc /* Memory Controlller Lock register */
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#define GFXVTBAR 0x5400 /* Base address for IGD */
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#define GFXVTBAR 0x5400 /* Base address for IGD */
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