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mb/intel/tglrvp: Update Power Limit2 minimum value 

Update Power Limit2 (PL2) minimum value to the same as maximum value.
DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.

BUG=None
BRANCH=None
TEST=Build and test on tglrvp system

Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2021-07-05 17:15:51 +05:30 committed by Felix Held
parent 270e25594f
commit 681a59d5c3
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -191,7 +191,7 @@ chip soc/intel/tigerlake
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 15000,
.min_power = 60000,
.max_power = 60000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,

2
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -195,7 +195,7 @@ chip soc/intel/tigerlake
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 9000,
.min_power = 40000,
.max_power = 40000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,