soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100

Use a read modify write sequence when setting the SPI_USE_SPI100 bit in
the SPI100_ENABLE register. This avoids clearing other bits in the
register which might cause instabilities of the SPI interface. The
reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and
doesn't zero out the other bits.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/soc/amd/stoneyridge/southbridge.c

@@ -242,7 +242,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
 				(fast << SPI_FAST_SPEED_NEW_SH) |
 				(alt << SPI_ALT_SPEED_NEW_SH) |
 				(tpm << SPI_TPM_SPEED_NEW_SH));
-	spi_write16(SPI100_ENABLE, SPI_USE_SPI100);
+	spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE));
 }
 
 static void sb_disable_4dw_burst(void)