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src: Get rid of device_t 

Use of device_t is deprecated.

Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-06-12 22:06:09 +02:00 committed by Patrick Georgi
parent c8a649c08f
commit 68c851bcd7
33 changed files with 189 additions and 76 deletions
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4
Documentation/Intel/SoC/soc.html
View File

@ -516,7 +516,7 @@ Use the following steps to debug the call to TempRamInit:
a "struct pci_operations" that specifies a routine to set the subsystem
IDs for the device. The routine might look something like this:
</p>
<pre><code>static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
<pre><code>static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
vendor = pci_read_config32(dev, PCI_VENDOR_ID);
@ -538,7 +538,7 @@ Use the following steps to debug the call to TempRamInit:
The memory map is built by the various PCI device drivers during the
BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically
specify the DRAM resources while the other drivers will typically specify
the IO resources. These resources are hung off the device_t data structure by
the IO resources. These resources are hung off the struct device *data structure by
src/device/device_util.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>.
</p>
<p>

12
src/lib/debug.c
View File

@ -22,7 +22,11 @@ static void print_debug_pci_dev(unsigned int dev)
static inline void print_pci_devices(void)
{
device_t dev;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev;
#else
struct device *dev;
#endif
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0x00, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
u32 id;
@ -56,7 +60,11 @@ static void dump_pci_device(unsigned int dev)
static inline void dump_pci_devices(void)
{
device_t dev;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev;
#else
struct device *dev;
#endif
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
u32 id;

43
src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
View File

@ -70,9 +70,9 @@ static uint32_t read_config32_dct(device_t dev, uint8_t node, uint8_t dct, uint3
if (is_fam15h()) {
uint32_t dword;
#ifdef __PRE_RAM__
device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
#else
device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
#endif
/* Select DCT */
@ -92,9 +92,9 @@ static void write_config32_dct(device_t dev, uint8_t node, uint8_t dct, uint32_t
if (is_fam15h()) {
uint32_t dword;
#ifdef __PRE_RAM__
device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
#else
device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
#endif
/* Select DCT */
@ -129,9 +129,9 @@ static uint32_t read_amd_dct_index_register_dct(device_t dev, uint8_t node, uint
if (is_fam15h()) {
uint32_t dword;
#ifdef __PRE_RAM__
device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
#else
device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
#endif
/* Select DCT */
@ -247,9 +247,12 @@ static uint64_t rdmsr_uint64_t(unsigned long index) {
return (((uint64_t)msr.hi) << 32) | ((uint64_t)msr.lo);
}
static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg) {
static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node,
uint8_t dct, uint8_t nb_pstate,
uint32_t reg)
{
uint32_t dword;
device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
/* Select DCT */
dword = pci_read_config32(dev_fn1, 0x10c);
@ -312,9 +315,9 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
/* Load data from DCTs into data structure */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
device_t dev_fn2 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 2));
device_t dev_fn3 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 3));
struct device *dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
struct device *dev_fn2 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 2));
struct device *dev_fn3 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 3));
/* Test for node presence */
if ((!dev_fn1) || (pci_read_config32(dev_fn1, PCI_VENDOR_ID) == 0xffffffff)) {
persistent_data->node[node].node_present = 0;
@ -524,9 +527,12 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
}
}
#else
static void write_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t value) {
static void write_config32_dct_nbpstate(pci_devfn_t dev, uint8_t node,
uint8_t dct, uint8_t nb_pstate,
uint32_t reg, uint32_t value)
{
uint32_t dword;
device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
/* Select DCT */
dword = pci_read_config32(dev_fn1, 0x10c);
@ -543,7 +549,9 @@ static void write_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t dct,
pci_write_config32(dev, reg, value);
}
static void write_amd_dct_index_register(device_t dev, uint32_t index_ctl_reg, uint32_t index, uint32_t value)
static void write_amd_dct_index_register(pci_devfn_t dev,
uint32_t index_ctl_reg, uint32_t index,
uint32_t value)
{
uint32_t dword;
@ -555,11 +563,14 @@ static void write_amd_dct_index_register(device_t dev, uint32_t index_ctl_reg, u
} while (!(dword & (1 << 31)));
}
static void write_amd_dct_index_register_dct(device_t dev, uint8_t node, uint8_t dct, uint32_t index_ctl_reg, uint32_t index, uint32_t value)
static void write_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node,
uint8_t dct,
uint32_t index_ctl_reg,
uint32_t index, uint32_t value)
{
if (is_fam15h()) {
uint32_t dword;
device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
/* Select DCT */
dword = pci_read_config32(dev_fn1, 0x10c);

6
src/soc/intel/apollolake/uart.c
View File

@ -60,7 +60,11 @@ static inline int invalid_uart_for_console(void)
void pch_uart_init(void)
{
uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
#else
struct device *uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
#endif
/* Get a 0-based pad index. See invalid_uart_for_console() above. */
const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;

6
src/soc/intel/broadwell/pmutil.c
View File

@ -452,7 +452,11 @@ int rtc_failure(void)
{
u8 reg8;
int rtc_failed;
device_t dev = PCH_DEV_LPC;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_LPC;
#else
struct device *dev = PCH_DEV_LPC;
#endif
reg8 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = reg8 & RTC_BATTERY_DEAD;

6
src/soc/intel/broadwell/romstage/uart.c
View File

@ -48,7 +48,11 @@ void pch_uart_init(void)
{
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
u32 gpiodf = 0x131f;
device_t dev;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev;
#else
struct device *dev;
#endif
/* Put UART in byte access mode for 16550 compatibility */
switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {

6
src/soc/intel/broadwell/smihandler.c
View File

@ -80,7 +80,11 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
device_t dev = PCI_DEV(bus, slot, func);
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCI_DEV(bus, slot, func);
#else
struct device *dev = PCI_DEV(bus, slot, func);
#endif
val = pci_read_config32(dev, PCI_VENDOR_ID);

6
src/soc/intel/broadwell/spi.c
View File

@ -266,7 +266,11 @@ void spi_init(void)
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
device_t dev = PCH_DEV_LPC;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_LPC;
#else
struct device *dev = PCH_DEV_LPC;
#endif
ich9_spi_regs *ich9_spi;
pci_read_config_dword(dev, 0xf0, &rcba);

7
src/soc/intel/cannonlake/lpc.c
View File

@ -140,8 +140,11 @@ void soc_pch_pirq_init(const struct device *dev)
pch_interrupt_routing[7] = config->pirqh_routing;
itss_irq_init(pch_interrupt_routing);
device_t irq_dev;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t irq_dev;
#else
struct device *irq_dev;
#endif
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;

6
src/soc/intel/cannonlake/uart.c
View File

@ -35,7 +35,11 @@
static const struct port {
struct pad_config pads[2]; /* just TX and RX */
device_t dev;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev;
#else
struct device *dev;
#endif
} uart_ports[] = {
{.dev = PCH_DEV_UART0,
.pads = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* RX */

6
src/soc/intel/common/block/acpi/acpi.c
View File

@ -164,7 +164,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
soc_fill_fadt(fadt);
}
unsigned long southbridge_write_acpi_tables(device_t device,
unsigned long southbridge_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
{
@ -224,7 +224,7 @@ __weak void acpi_create_gnvs(struct global_nvs_t *gnvs)
{
}
void southbridge_inject_dsdt(device_t device)
void southbridge_inject_dsdt(struct device *device)
{
struct global_nvs_t *gnvs;
@ -407,7 +407,7 @@ __weak void soc_power_states_generation(int core_id,
{
}
void generate_cpu_entries(device_t device)
void generate_cpu_entries(struct device *device)
{
int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS;
int plen = 6;

6
src/soc/intel/common/block/cpu/mp_init.c
View File

@ -31,7 +31,7 @@
static const void *microcode_patch;
/* SoC override function */
__weak void soc_core_init(device_t dev)
__weak void soc_core_init(struct device *dev)
{
/* no-op */
}
@ -41,7 +41,7 @@ __weak void soc_init_cpus(struct bus *cpu_bus)
/* no-op */
}
static void init_one_cpu(device_t dev)
static void init_one_cpu(struct device *dev)
{
soc_core_init(dev);
intel_microcode_load_unlocked(microcode_patch);
@ -121,7 +121,7 @@ void get_microcode_info(const void **microcode, int *parallel)
static void init_cpus(void *unused)
{
device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
assert(dev != NULL);
microcode_patch = intel_microcode_find();

6
src/soc/intel/common/block/cse/cse.c
View File

@ -80,7 +80,11 @@ struct cse_device {
void heci_init(uintptr_t tempbar)
{
struct cse_device *cse = car_get_var_ptr(&g_cse);
device_t dev = PCH_DEV_CSE;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_CSE;
#else
struct device *dev = PCH_DEV_CSE;
#endif
u8 pcireg;
/* Assume it is already initialized, nothing else to do */

30
src/soc/intel/common/block/fast_spi/fast_spi.c
View File

@ -34,7 +34,11 @@
*/
void *fast_spi_get_bar(void)
{
device_t dev = PCH_DEV_SPI;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_SPI;
#else
struct device *dev = PCH_DEV_SPI;
#endif
uintptr_t bar;
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@ -51,7 +55,11 @@ void *fast_spi_get_bar(void)
*/
void fast_spi_init(void)
{
device_t dev = PCH_DEV_SPI;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_SPI;
#else
struct device *dev = PCH_DEV_SPI;
#endif
uint8_t bios_cntl;
bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
@ -71,7 +79,11 @@ void fast_spi_init(void)
*/
static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit)
{
device_t dev = PCH_DEV_SPI;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_SPI;
#else
struct device *dev = PCH_DEV_SPI;
#endif
uint8_t bc_cntl;
assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
@ -253,7 +265,11 @@ void fast_spi_cache_bios_region(void)
*/
void fast_spi_early_init(uintptr_t spi_base_address)
{
device_t dev = PCH_DEV_SPI;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_SPI;
#else
struct device *dev = PCH_DEV_SPI;
#endif
uint8_t pcireg;
/* Assign Resources to SPI Controller */
@ -285,7 +301,11 @@ bool fast_spi_wpd_status(void)
/* Enable SPI Write Protect. */
void fast_spi_enable_wp(void)
{
device_t dev = PCH_DEV_SPI;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_SPI;
#else
struct device *dev = PCH_DEV_SPI;
#endif
uint8_t bios_cntl;
bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);

12
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -167,7 +167,11 @@ bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size)
*/
static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit)
{
device_t dev = PCH_DEV_LPC;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_LPC;
#else
struct device *dev = PCH_DEV_LPC;
#endif
uint8_t bc_cntl;
assert(IS_POWER_OF_2(bios_cntl_bit));
@ -210,7 +214,11 @@ void lpc_set_eiss(void)
*/
void lpc_set_serirq_mode(enum serirq_mode mode)
{
device_t dev = PCH_DEV_LPC;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_LPC;
#else
struct device *dev = PCH_DEV_LPC;
#endif
uint8_t scnt;
scnt = pci_read_config8(dev, LPC_SERIRQ_CTL);

6
src/soc/intel/common/block/pcr/pcr.c
View File

@ -254,7 +254,11 @@ static int pcr_wait_for_completion(device_t dev)
int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data,
uint8_t *response)
{
device_t dev = PCH_DEV_P2SB;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_P2SB;
#else
struct device *dev = PCH_DEV_P2SB;
#endif
uint32_t sbi_data;
uint16_t sbi_status;
uint16_t sbi_rid;

6
src/soc/intel/common/block/smm/smihandler.c
View File

@ -134,7 +134,11 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
device_t dev = PCI_DEV(bus, slot, func);
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCI_DEV(bus, slot, func);
#else
struct device *dev = PCI_DEV(bus, slot, func);
#endif
if (!smihandler_soc_disable_busmaster(dev))
continue;

6
src/soc/intel/common/block/uart/uart.c
View File

@ -59,7 +59,11 @@ __weak device_t pch_uart_get_debug_controller(void)
bool uart_debug_controller_is_initialized(void)
{
device_t dev;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev;
#else
struct device *dev;
#endif
uintptr_t base;
dev = pch_uart_get_debug_controller();

7
src/soc/intel/denverton_ns/bootblock/uart.c
View File

@ -31,8 +31,11 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func,
u32 mmio_base)
{
register uint16_t reg16;
device_t uart_dev = PCI_DEV(bus, dev, func);
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t uart_dev = PCI_DEV(bus, dev, func);
#else
struct device *uart_dev = PCI_DEV(bus, dev, func);
#endif
/* We're using MMIO for HSUARTs. This section is needed for logging
* from FSP only

7
src/soc/intel/denverton_ns/memmap.c
View File

@ -30,8 +30,11 @@
/* Returns base of requested region encoded in the system agent. */
static inline uintptr_t system_agent_region_base(size_t reg)
{
device_t dev = SA_DEV_ROOT;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = SA_DEV_ROOT;
#else
struct device *dev = SA_DEV_ROOT;
#endif
/* All regions concerned for have 1 MiB alignment. */
return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);
}

12
src/soc/intel/denverton_ns/romstage.c
View File

@ -50,7 +50,11 @@ static void display_fsp_smbios_memory_info_hob(void)
static void early_pmc_init(void)
{
/* PMC (B0:D31:F2). */
device_t dev = PCH_PMC_DEV;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_PMC_DEV;
#else
struct device *dev = PCH_PMC_DEV;
#endif
/* Is PMC present */
if (pci_read_config16(dev, 0) == 0xffff) {
@ -99,7 +103,11 @@ static void early_pmc_init(void)
static void early_tco_init(void)
{
/* SMBUS (B0:D31:F4). */
device_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
#else
struct device *dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
#endif
/* Configure TCO base address */
if (pci_read_config16(dev, TCOBASE) == 0xffff) {

6
src/soc/intel/denverton_ns/smihandler.c
View File

@ -65,7 +65,11 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
device_t dev = PCI_DEV(bus, slot, func);
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCI_DEV(bus, slot, func);
#else
struct device *dev = PCI_DEV(bus, slot, func);
#endif
val = pci_read_config32(dev, PCI_VENDOR_ID);

2
src/soc/intel/skylake/bootblock/pch.c
View File

@ -46,7 +46,7 @@
static void enable_p2sbbar(void)
{
device_t dev = PCH_DEV_P2SB;
pci_devfn_t dev = PCH_DEV_P2SB;
/* Enable PCR Base address in PCH */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);

10
src/soc/intel/skylake/bootblock/report_platform.c
View File

@ -104,12 +104,12 @@ static struct {
{ PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" },
};
static uint8_t get_dev_revision(device_t dev)
static uint8_t get_dev_revision(pci_devfn_t dev)
{
return pci_read_config8(dev, PCI_REVISION_ID);
}
static uint16_t get_dev_id(device_t dev)
static uint16_t get_dev_id(pci_devfn_t dev)
{
return pci_read_config16(dev, PCI_DEVICE_ID);
}
@ -171,7 +171,7 @@ static void report_cpu_info(void)
static void report_mch_info(void)
{
int i;
device_t dev = SA_DEV_ROOT;
pci_devfn_t dev = SA_DEV_ROOT;
uint16_t mchid = get_dev_id(dev);
uint8_t mch_revision = get_dev_revision(dev);
const char *mch_type = "Unknown";
@ -190,7 +190,7 @@ static void report_mch_info(void)
static void report_pch_info(void)
{
int i;
device_t dev = PCH_DEV_LPC;
pci_devfn_t dev = PCH_DEV_LPC;
uint16_t lpcid = get_dev_id(dev);
const char *pch_type = "Unknown";
@ -207,7 +207,7 @@ static void report_pch_info(void)
static void report_igd_info(void)
{
int i;
device_t dev = SA_DEV_IGD;
pci_devfn_t dev = SA_DEV_IGD;
uint16_t igdid = get_dev_id(dev);
const char *igd_type = "Unknown";

6
src/soc/intel/skylake/pmc.c
View File

@ -31,7 +31,11 @@ void pmc_set_disb(void)
{
/* Set the DISB after DRAM init */
u32 disb_val;
device_t dev = PCH_DEV_PMC;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_PMC;
#else
struct device *dev = PCH_DEV_PMC;
#endif
disb_val = pci_read_config32(dev, GEN_PMCON_A);
disb_val |= DISB;

8
src/soc/intel/skylake/pmutil.c
View File

@ -19,8 +19,6 @@
* and the differences between PCH variants.
*/
#define __SIMPLE_DEVICE__
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
@ -232,7 +230,11 @@ int rtc_failure(void)
u8 reg8;
int rtc_failed;
/* PMC Controller Device 0x1F, Func 02 */
device_t dev = PCH_DEV_PMC;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev = PCH_DEV_PMC;
#else
struct device *dev = PCH_DEV_PMC;
#endif
reg8 = pci_read_config8(dev, GEN_PMCON_B);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {

4
src/southbridge/intel/bd82x6x/early_pch_common.c
View File

@ -66,9 +66,9 @@ int southbridge_detect_s3_resume(void)
int rtc_failure(void)
{
#if defined(__SIMPLE_DEVICE__)
device_t dev = PCI_DEV(0, 0x1f, 0);
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
#else
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
}

4
src/southbridge/intel/bd82x6x/early_usb_mrc.c
View File

@ -32,8 +32,8 @@
*/
void enable_usb_bar(void)
{
device_t usb0 = PCH_EHCI1_DEV;
device_t usb1 = PCH_EHCI2_DEV;
pci_devfn_t usb0 = PCH_EHCI1_DEV;
pci_devfn_t usb1 = PCH_EHCI2_DEV;
u32 cmd;
/* USB Controller 1 */

4
src/southbridge/intel/bd82x6x/pch.c
View File

@ -36,7 +36,7 @@ int pch_silicon_revision(void)
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
#else
device_t dev;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
@ -53,7 +53,7 @@ int pch_silicon_type(void)
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
#else
device_t dev;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif

5
src/southbridge/intel/common/spi.c
View File

@ -298,15 +298,14 @@ void spi_init(void)
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
device_t dev;
ich9_spi_regs *ich9_spi;
ich7_spi_regs *ich7_spi;
uint16_t hsfs;
#ifdef __SIMPLE_DEVICE__
dev = PCI_DEV(0, 31, 0);
pci_devfn_t dev = PCI_DEV(0, 31, 0);
#else
dev = dev_find_slot(0, PCI_DEVFN(31, 0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0));
#endif
pci_read_config_dword(dev, 0xf0, &rcba);

4
src/southbridge/intel/lynxpoint/pmutil.c
View File

@ -558,9 +558,9 @@ void disable_gpe(u32 mask)
int rtc_failure(void)
{
#if defined(__SIMPLE_DEVICE__)
device_t dev = PCI_DEV(0, 31, 0);
pci_devfn_t dev = PCI_DEV(0, 31, 0);
#else
device_t dev = dev_find_slot(0, PCI_DEVFN(31, 0));
struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0));
#endif
return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
}

2
src/southbridge/intel/lynxpoint/smihandler.c
View File

@ -75,7 +75,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
device_t dev = PCI_DEV(bus, slot, func);
pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);

4
util/autoport/main.go
View File

@ -771,12 +771,12 @@ func main() {
}
mainboard.WriteString("\n")
if MainboardInit != "" {
mainboard.WriteString(`static void mainboard_init(device_t dev)
mainboard.WriteString(`static void mainboard_init(struct device *dev)
{
` + MainboardInit + "}\n\n")
}
if MainboardInit != "" || MainboardEnable != "" {
mainboard.WriteString("static void mainboard_enable(device_t dev)\n{\n")
mainboard.WriteString("static void mainboard_enable(struct device *dev)\n{\n")
if MainboardInit != "" {
mainboard.WriteString("\tdev->ops->init = mainboard_init;\n\n")
}