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drivers/aspeed: Fix AST2400 POST failure without BMC FW or VBIOS 

This patch is from Linux, commit 3856081eede2. The commit message there
is:

> commit 3856081eede297b617560b85e948cfb00bb395ec
> Author: Y.C. Chen <yc_chen@aspeedtech.com>
> Date:   Thu Feb 23 15:52:33 2017 +0800
>
>     drm/ast: Fix AST2400 POST failure without BMC FW or VBIOS
>
>     The current POST code for the AST2300/2400 family doesn't work properly
>     if the chip hasn't been initialized previously by either the BMC own FW
>     or the VBIOS. This fixes it.
>
>     Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
>     Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>     Tested-by: Y.C. Chen <yc_chen@aspeedtech.com>
>     Acked-by: Joel Stanley <joel@jms.id.au>
>     Cc: <stable@vger.kernel.org>
>     Signed-off-by: Dave Airlie <airlied@redhat.com>

Tested on a Supermicro X10SLM+-F with an AST 2400 where the BMC flash
chip has been completely erased. Before the patch, the display resembled
a rainbow. After the patch, the display works well.

Original-Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
Original-Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Original-Tested-by: Y.C. Chen <yc_chen@aspeedtech.com>
Original-Signed-off-by: Dave Airlie <airlied@redhat.com>

Change-Id: I72efcf907fbd1263fe21d4f36fe900b305419c44
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Tristan Corrick 2018-12-03 16:17:47 +13:00 committed by Patrick Georgi
parent 5ff742c740
commit 68dc36c9b3
1 changed files with 35 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
src/drivers/aspeed/common/ast_post.c
View File

@ -1693,12 +1693,44 @@ static void ast_init_dram_2300(struct drm_device *dev)
temp |= 0x73;
ast_write32(ast, 0x12008, temp);
param.dram_freq = 396;
param.dram_type = AST_DDR3;
temp = ast_mindwm(ast, 0x1e6e2070);
if (temp & 0x01000000)
param.dram_type = AST_DDR2;
param.dram_chipid = ast->dram_type;
param.dram_freq = ast->mclk;
param.vram_size = ast->vram_size;
switch (temp & 0x18000000) {
case 0:
param.dram_chipid = AST_DRAM_512Mx16;
break;
default:
case 0x08000000:
param.dram_chipid = AST_DRAM_1Gx16;
break;
case 0x10000000:
param.dram_chipid = AST_DRAM_2Gx16;
break;
case 0x18000000:
param.dram_chipid = AST_DRAM_4Gx16;
break;
}
switch (temp & 0x0c) {
default:
case 0x00:
param.vram_size = AST_VIDMEM_SIZE_8M;
break;
case 0x04:
param.vram_size = AST_VIDMEM_SIZE_16M;
break;
case 0x08:
param.vram_size = AST_VIDMEM_SIZE_32M;
break;
case 0x0c:
param.vram_size = AST_VIDMEM_SIZE_64M;
break;
}
if (param.dram_type == AST_DDR3) {
get_ddr3_info(ast, &param);