soc/amd/common: Fix some white spaces issues

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I54438978db13ba00188e53239f7034d1b258e912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/amd/common/block/acpi/ivrs.c

@@ -62,7 +62,7 @@ static unsigned long ivhd_describe_hpet(unsigned long current)
 static unsigned long ivhd_describe_f0_device(unsigned long current,
 						uint16_t dev_id, uint8_t datasetting)
 {
-	ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *) current;
+	ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *)current;
 
 	ivhd_f0->type = IVHD_DEV_VARIABLE;
 	ivhd_f0->dev_id = dev_id;
@@ -287,7 +287,7 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs)
 	ivhd_11->iommu_base_high = ivrs->ivhd.iommu_base_high;
 	ivhd_11->pci_segment_group = 0x0000;
 	ivhd_11->iommu_info = ivrs->ivhd.iommu_info;
-	ivhd11_attr_ptr = (ivhd11_iommu_attr_t *) &ivrs->ivhd.iommu_feature_info;
+	ivhd11_attr_ptr = (ivhd11_iommu_attr_t *)&ivrs->ivhd.iommu_feature_info;
 	ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters;
 	ivhd_11->iommu_attributes.perf_counter_banks = ivhd11_attr_ptr->perf_counter_banks;
 	ivhd_11->iommu_attributes.msi_num_ppr = ivhd11_attr_ptr->msi_num_ppr;

src/soc/amd/common/block/acpimmio/biosram.c

@@ -75,8 +75,8 @@ void save_uma_size(uint32_t size)
 
 void save_uma_base(uint64_t base)
 {
-	biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
+	biosram_write32(BIOSRAM_UMA_BASE, (uint32_t)base);
-	biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
+	biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t)(base >> 32));
 }
 
 uint32_t get_uma_size(void)

src/soc/amd/common/block/cpu/noncar/early_cache.c

@@ -60,7 +60,7 @@ void early_cache_setup(void)
 
 	wrmsr(SYSCFG_MSR, sys_cfg);
 
-	var_mtrr_set(&mtrr_ctx.ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK);
+	var_mtrr_set(&mtrr_ctx.ctx, 0, ALIGN_DOWN(top_mem.lo, 8 * MiB), MTRR_TYPE_WRBACK);
 	/* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */
 	var_mtrr_set(&mtrr_ctx.ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
 

src/soc/amd/common/block/pci/amd_pci_util.c

@@ -67,11 +67,11 @@ void write_pci_int_table(void)
 	 */
 	for (i = 0 ; i < limit; i++) {
 		byte = idx_name[i].index;
-		write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]);
+		write_pci_int_idx(byte, 0, (u8)picr_data_ptr[byte]);
 		printk(BIOS_DEBUG, "0x%02X\t\t%-20s 0x%02X\t",
 				byte, idx_name[i].name,
 				read_pci_int_idx(byte, 0));
-		write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]);
+		write_pci_int_idx(byte, 1, (u8)intr_data_ptr[byte]);
 		printk(BIOS_DEBUG, "0x%02X\n", read_pci_int_idx(byte, 1));
 	}
 }

src/soc/amd/common/fsp/fsp_validate.c

@@ -16,7 +16,7 @@ void soc_validate_fspm_header(const struct fsp_header *hdr)
 {
 	struct amd_image_revision *rev;
 
-	rev = (struct amd_image_revision *) &(hdr->image_revision);
+	rev = (struct amd_image_revision *)&(hdr->image_revision);
 
 	/* Check if the image fits into the reserved memory region */
 	if (hdr->image_size > CONFIG_FSP_M_SIZE)

src/soc/amd/common/pi/amd_late_init.c

@@ -81,8 +81,8 @@ static void print_dimm_info(const struct dimm_info *dimm)
 	       dimm->serial[1],
 	       dimm->serial[2],
 	       dimm->serial[3],
-	       strlen((char *) dimm->module_part_number),
+	       strlen((char *)dimm->module_part_number),
-	       (char *) dimm->module_part_number
+	       (char *)dimm->module_part_number
 	);
 }
 
@@ -120,9 +120,9 @@ static void print_dmi_info(const TYPE17_DMI_INFO *dmi17)
 	       dmi17->FormFactor,
 	       dmi17->DeviceLocator,
 	       dmi17->BankLocator,
-	       strlen((char *) dmi17->SerialNumber),
+	       strlen((char *)dmi17->SerialNumber),
 	       dmi17->SerialNumber,
-	       strlen((char *) dmi17->PartNumber),
+	       strlen((char *)dmi17->PartNumber),
 	       dmi17->PartNumber
 	);
 }

src/soc/amd/common/pi/heapmanager.c

@@ -259,7 +259,7 @@ AGESA_STATUS agesa_AllocateBuffer(uint32_t Func, uintptr_t Data,
 
 		BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr
 					+ BestFitNodeOffset);
-		BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr +
+		BestFitPrevNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr +
 							BestFitPrevNodeOffset);
 
 		/*
@@ -268,7 +268,7 @@ AGESA_STATUS agesa_AllocateBuffer(uint32_t Func, uintptr_t Data,
 		 */
 		if (BestFitNodePtr->BufferSize > MinimumSize) {
 			NextFreeOffset = BestFitNodeOffset + MinimumSize;
-			NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr +
+			NextFreePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr +
 				       NextFreeOffset);
 			NextFreePtr->BufferSize = BestFitNodeSize - MinimumSize;
 

src/soc/amd/common/pi/image.c

@@ -35,7 +35,7 @@ void *amd_find_image(const void *start_address, const void *end_address,
 
 	while ((current_ptr >= start) && (current_ptr < end)) {
 		if (IMAGE_SIGNATURE == *((uint32_t *)current_ptr)) {
-			image_ptr = (AMD_IMAGE_HEADER *) current_ptr;
+			image_ptr = (AMD_IMAGE_HEADER *)current_ptr;
 
 			/* Check if the image has the desired module */
 			if (validate_image((void *)image_ptr->ModuleInfoOffset,

src/soc/amd/common/psp_verstage/vboot_crypto.c

@@ -47,7 +47,7 @@ vb2_error_t vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, uint32_
 vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
 {
 	uint32_t retval;
-	sha_op.Data = (uint8_t *) buf;
+	sha_op.Data = (uint8_t *)buf;
 
 	if (!sha_op_size_remaining) {
 		printk(BIOS_ERR, "got more data than expected.\n");