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coreboot_tables: Add CBMEM ID and tag for MTC 

BUG=chrome-os-partner:41125
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt

Change-Id: Ia95b2a21863df5c3d6c08e9a134618db03a58775
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8462a33c62ab34d0f5049fc3a7c5c2ee8e5e2e4c
Original-Change-Id: Ie48a9a776b1c3ad30acf924c3d073acc8f2a8eda
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276779
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10562
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Furquan Shaikh 2015-06-10 20:43:24 -07:00 committed by Patrick Georgi
parent 2da9524aaf
commit 69139e0e2a
2 changed files with 3 additions and 0 deletions
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1
src/include/boot/coreboot_tables.h
View File

@ -229,6 +229,7 @@ struct lb_gpios {
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_DMA 0x0022
#define LB_TAG_RAM_OOPS 0x0023
#define LB_TAG_MTC 0x002b
struct lb_range {
uint32_t tag;
uint32_t size;

2
src/include/cbmem_id.h
View File

@ -43,6 +43,7 @@
#define CBMEM_ID_MEMINFO 0x494D454D
#define CBMEM_ID_MPTABLE 0x534d5054
#define CBMEM_ID_MRCDATA 0x4d524344
#define CBMEM_ID_MTC 0xcb31d31c
#define CBMEM_ID_NONE 0x00000000
#define CBMEM_ID_PIRQ 0x49525154
#define CBMEM_ID_POWER_STATE 0x50535454
@ -88,6 +89,7 @@
{ CBMEM_ID_MEMINFO, "MEM INFO " }, \
{ CBMEM_ID_MPTABLE, "SMP TABLE " }, \
{ CBMEM_ID_MRCDATA, "MRC DATA " }, \
{ CBMEM_ID_MTC, "MTC " }, \
{ CBMEM_ID_PIRQ, "IRQ TABLE " }, \
{ CBMEM_ID_POWER_STATE, "POWER STATE" }, \
{ CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \