mb/google/volteer: Add GPIO to collis support
Add support for gpio driver for collis BUG=b:182227204 TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ief225093bf93137384b64327a1c66576c9a5193a Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
FrankChu
Nick Vaccaro
parent
3647e86862
commit
6943ada500
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@ -1,3 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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romstage-y += memory.c
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <variant/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
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/* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */
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PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
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/* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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PAD_CFG_GPO(GPP_A13, 1, DEEP),
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/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* A18 : DDSP_HPDB ==> HDMI_HPD */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_A21, 1, DEEP),
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/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
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PAD_CFG_GPO(GPP_A22, 1, DEEP),
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/* B2 : VRALERT# ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_B2, 1, DEEP),
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/* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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/* B22 : GSPI1_MOSI ==> NC */
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PAD_NC(GPP_B22, NONE),
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/* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
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PAD_NC(GPP_B23, DN_20K),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C2 : SMBALERT# ==> GPP_C2_STRAP */
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PAD_NC(GPP_C2, DN_20K),
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/* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */
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PAD_NC(GPP_C5, DN_20K),
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/* C7 : SML1DATA ==> EN_USI_CHARGE */
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PAD_CFG_GPO(GPP_C7, 1, DEEP),
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/* C10 : UART0_RTS# ==> USI_RST_L */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C11 : UART0_CTS# ==> TOUCHSCREEN_STOP_L_R */
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PAD_CFG_GPO(GPP_C11, 1, DEEP),
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/* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */
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PAD_CFG_GPO(GPP_C13, 1, DEEP),
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/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* D0 : ISH_GP0 ==> ISH_IMU_INT_L */
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PAD_CFG_GPI(GPP_D0, NONE, DEEP),
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/* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */
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PAD_CFG_GPI(GPP_D1, NONE, DEEP),
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/* D2 : ISH_GP2 ==> ISH_LID_OPEN */
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PAD_CFG_GPI(GPP_D2, NONE, DEEP),
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/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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/* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */
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PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7),
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/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */
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PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
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/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_D16, 1, DEEP),
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/* E1 : SPI1_IO2 ==> PEN_DET_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
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/* E3 : CPU_GP0 ==> USI_REPORT_EN */
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PAD_CFG_GPO(GPP_E3, 1, DEEP),
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/* E7 : CPU_GP1 ==> USI_INT */
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PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
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/* E10 : SPI1_CS# ==> NC */
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PAD_NC(GPP_E10, NONE),
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/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
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PAD_CFG_GPI(GPP_E11, NONE, DEEP),
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/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
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PAD_CFG_GPI(GPP_E12, NONE, DEEP),
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/* E13 : SPI1_MOSI_IO0 ==> NC */
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PAD_NC(GPP_E13, NONE),
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/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
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/* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */
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PAD_CFG_GPO(GPP_E16, 1, DEEP),
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/* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E17, NONE, PLTRST),
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/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
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PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),
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/* E20 : DDP2_CTRLCLK ==> NC */
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PAD_NC(GPP_E20, NONE),
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/* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */
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PAD_CFG_GPO(GPP_E22, 1, DEEP),
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/* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */
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PAD_CFG_GPO(GPP_E23, 1, DEEP),
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/* F7 : GPPF7_STRAP */
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PAD_NC(GPP_F7, DN_20K),
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/* F11 : THC1_SPI2_CLK ==> NC */
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PAD_NC(GPP_F11, NONE),
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/* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */
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PAD_CFG_GPO(GPP_F12, 1, DEEP),
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/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
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PAD_CFG_GPO(GPP_F13, 1, DEEP),
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/* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */
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PAD_CFG_GPO(GPP_F16, 1, DEEP),
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/* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F17, NONE, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */
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PAD_CFG_GPO(GPP_F18, 1, DEEP),
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/* H0 : GPPH0_BOOT_STRAP1 */
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PAD_NC(GPP_H0, DN_20K),
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/* H1 : GPPH1_BOOT_STRAP2 */
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PAD_NC(GPP_H1, DN_20K),
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/* H2 : GPPH2_BOOT_STRAP3 */
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PAD_NC(GPP_H2, DN_20K),
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/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H3, 1, DEEP),
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/* H10 : SRCCLKREQ4# ==> NC */
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PAD_NC(GPP_H10, NONE),
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/* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */
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PAD_CFG_GPI(GPP_H13, NONE, DEEP),
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/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
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/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
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/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
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PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
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/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
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/* R5 : HDA_SDI1 ==> HP_INT_L */
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PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH),
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/* S4 : SNDW2_CLK ==> DMIC_CLK1 */
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PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
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/* S5 : SNDW2_DATA ==> DMIC_DATA1 */
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PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
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/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
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PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
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/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
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/* GPD6: SLP_A# ==> NC */
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PAD_NC(GPD6, NONE),
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/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
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PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
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};
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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/* B2 : VRALERT# ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_B2, 1, DEEP),
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/* B11 : PMCALERT# ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
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/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
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PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_D16, 1, DEEP),
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/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
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PAD_CFG_GPI(GPP_E12, NONE, DEEP),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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