soc/intel/cannonlake: add gpio files to make

Adds gpio.c to romstage and ramstage.
Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS.

Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Nick Vaccaro 2017-08-29 19:25:23 -07:00 committed by Aaron Durbin
parent f516dd8b40
commit 69b5cdb33c
2 changed files with 3 additions and 0 deletions

View File

@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select C_ENVIRONMENT_BOOTBLOCK select C_ENVIRONMENT_BOOTBLOCK
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select GENERIC_GPIO_LIB
select HAVE_HARD_RESET select HAVE_HARD_RESET
select HAVE_INTEL_FIRMWARE select HAVE_INTEL_FIRMWARE
select HAVE_MONOTONIC_TIMER select HAVE_MONOTONIC_TIMER

View File

@ -19,6 +19,7 @@ bootblock-y += memmap.c
bootblock-y += spi.c bootblock-y += spi.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-y += gpio.c
romstage-y += gspi.c romstage-y += gspi.c
romstage-y += memmap.c romstage-y += memmap.c
romstage-y += pmutil.c romstage-y += pmutil.c
@ -28,6 +29,7 @@ romstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-y += chip.c ramstage-y += chip.c
ramstage-y += cpu.c ramstage-y += cpu.c
ramstage-y += gpio.c
ramstage-y += gspi.c ramstage-y += gspi.c
ramstage-y += memmap.c ramstage-y += memmap.c
ramstage-y += pmutil.c ramstage-y += pmutil.c