69b5cdb33c
Adds gpio.c to romstage and ramstage. Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS. Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
53 lines
1.4 KiB
Makefile
53 lines
1.4 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/cpu.c
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bootblock-y += bootblock/pch.c
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bootblock-y += pmutil.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += gpio.c
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bootblock-y += gspi.c
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bootblock-y += memmap.c
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bootblock-y += spi.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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romstage-y += gpio.c
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romstage-y += gspi.c
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romstage-y += memmap.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += spi.c
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romstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += memmap.c
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ramstage-y += pmutil.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += spi.c
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ramstage-y += systemagent.c
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ramstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += vr_config.c
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postcar-y += memmap.c
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postcar-y += pmutil.c
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postcar-y += spi.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
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endif
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