17 commits

Author	SHA1	Message	Date
Nick Vaccaro	69b5cdb33c	soc/intel/cannonlake: add gpio files to make ... Adds gpio.c to romstage and ramstage. Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS. Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-09-01 17:26:56 +00:00
Pratik Prajapati	9027e1ba2f	soc/intel/cannonlake: Init UPD params based on config ... Initialize UPD params based upon config Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21175 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2017-08-25 18:24:33 +00:00
Pratik Prajapati	01eda28bff	soc/intel/cannonlake: Add cpu.c and MP init support ... Add initial MP init support. This boots up all CPUs. Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21081 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2017-08-24 16:06:30 +00:00
Lijian Zhao	b3dfcb863c	soc/intel/cannonlake: Enable common PMC code for CNL ... This update changes Cannonlake to use the new common PMC code. This will help to reduce code duplication and streamline code bring up. Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-08-21 20:37:57 +00:00
Lijian Zhao	321111774c	soc/intel/cannonlake: Add SPI flash controller driver ... Add SPI driver code for the SPI flash controller, including both fast_spi and generic_spi. Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-08-17 21:50:58 +00:00
Lijian Zhao	2f764f7dfe	soc/intel/cannonlake: Call into FSP siliconinit ... The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. This patch was merged too early, and reverted. Originally reviewed on https://review.coreboot.org/#/c/20581 Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20687 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2017-08-15 20:21:31 +00:00
Lijian Zhao	8465a81e81	soc/intel/cannonlake: Add postcar stage support ... Initialize postcar frame once finish FSP memoryinit This patch was merged too early and reverted. Originally reviewed on https://review.coreboot.org/#/c/20534 Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20688 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2017-08-15 20:21:22 +00:00
Lijian Zhao	aa3d78d5e6	soc/intel/cannonlake: Add ramstage SystemAgent support ... Revere memory resource within SA, also perform necessary routine for initialization during ramstage. Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20914 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2017-08-09 20:06:27 +00:00
Lijian Zhao	e88fa490a5	soc/intel/cannonlake: Add memory map support ... Calculate the top of ram from output of Fsp reserved memory range. Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2017-08-07 17:53:13 +00:00
Martin Roth	80358a1f47	Revert "soc/intel/cannonlake: Add postcar stage support" ... This reverts commit 399c022a8c. This was merged too early. I'll repost it. Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20686 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2017-07-21 17:39:10 +00:00
Martin Roth	70de396958	Revert "soc/intel/cannonlake: Call into FSP siliconinit" ... This reverts commit dbe7f893c0. This was merged too early. I'll repost it. Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2017-07-21 17:32:07 +00:00
Lijian Zhao	dbe7f893c0	soc/intel/cannonlake: Call into FSP siliconinit ... The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-07-21 15:56:16 +00:00
Lijian Zhao	399c022a8c	soc/intel/cannonlake: Add postcar stage support ... Initialize postcar frame once finish FSP memoryinit Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-07-21 15:55:40 +00:00
Lijian Zhao	0ade3133a0	soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit ... The following minimal changes are needed to make system boot until FSP memoryinit got called. 1. Program SA BARs 2. Assume previous power state is S0. Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-07-19 23:06:07 +00:00
Lijian Zhao	acfc149f7b	soc/intel/cannonlake: Add microcode support ... Microcode needs to be loaded prior to FSP initialization. Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20484 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2017-07-19 16:16:44 +00:00
Andrey Petrov	9f244a5494	soc/intel/cannonlake: Add Makefile ... This enables building working bootblock and non-functional romstage and ramstage. Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-07-13 19:28:53 +00:00
Lijian Zhao	81096041b8	soc/intel/cannonlake: Add initial dummy directory ... Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-06-29 14:50:38 +00:00