soc/intel/cannonlake: add gpio files to make
Adds gpio.c to romstage and ramstage. Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS. Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
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select BOOT_DEVICE_SUPPORTS_WRITES
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select BOOT_DEVICE_SUPPORTS_WRITES
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select C_ENVIRONMENT_BOOTBLOCK
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select C_ENVIRONMENT_BOOTBLOCK
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select GENERIC_GPIO_LIB
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select HAVE_HARD_RESET
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select HAVE_HARD_RESET
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select HAVE_INTEL_FIRMWARE
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select HAVE_INTEL_FIRMWARE
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select HAVE_MONOTONIC_TIMER
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select HAVE_MONOTONIC_TIMER
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@ -19,6 +19,7 @@ bootblock-y += memmap.c
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bootblock-y += spi.c
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bootblock-y += spi.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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romstage-y += gpio.c
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romstage-y += gspi.c
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romstage-y += gspi.c
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romstage-y += memmap.c
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romstage-y += memmap.c
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romstage-y += pmutil.c
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romstage-y += pmutil.c
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@ -28,6 +29,7 @@ romstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += chip.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += cpu.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += gspi.c
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ramstage-y += memmap.c
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ramstage-y += memmap.c
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ramstage-y += pmutil.c
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ramstage-y += pmutil.c
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