nb/intel/sandybridge/raminit: Advertise correct frequency
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the reference clock can be 100Mhz. Decode the register and use the reference clock to calculate the selected DDR frequency. Tested on Lenovo T430. Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -123,14 +123,17 @@ static void fill_smbios17(ramctr_timing *ctrl)
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static void report_memory_config(void)
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static void report_memory_config(void)
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{
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{
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u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS];
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u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS];
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int i;
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int i, refclk;
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addr_decoder_common = MCHBAR32(0x5000);
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addr_decoder_common = MCHBAR32(0x5000);
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addr_decode_ch[0] = MCHBAR32(0x5004);
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addr_decode_ch[0] = MCHBAR32(0x5004);
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addr_decode_ch[1] = MCHBAR32(0x5008);
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addr_decode_ch[1] = MCHBAR32(0x5008);
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refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
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printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk);
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
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(MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100);
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3, (addr_decoder_common >> 2) & 3,
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addr_decoder_common & 3, (addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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(addr_decoder_common >> 4) & 3);
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