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soc/amd/stoneyridge: Rearrange sb_util.c 

In preparation to move code to a common directory, rearrange some of
the functions in sb_util.c.  Add various comments.  This change should
have no functional differences.

Change-Id: I1ad55a4a14a27e45459dcaf2fcc7449e29da6d4b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Marshall Dawson 2019-05-05 12:17:53 -06:00 committed by Martin Roth
parent 5de4771360
commit 6ac87c4986
1 changed files with 163 additions and 126 deletions
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289
src/soc/amd/stoneyridge/sb_util.c
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@ -18,34 +18,65 @@
#include <arch/acpi.h>
#include <soc/southbridge.h>
void pm_write8(u8 reg, u8 value)
/* smbus pci read/write - access registers at 0xfed80000 - currently unused */
/* smi read/write - access registers at 0xfed80200 */
uint8_t smi_read8(uint8_t offset)
{
write8((void *)(ACPIMMIO_PMIO_BASE + reg), value);
return read8((void *)(ACPIMMIO_SMI_BASE + offset));
}
uint16_t smi_read16(uint8_t offset)
{
return read16((void *)(ACPIMMIO_SMI_BASE + offset));
}
uint32_t smi_read32(uint8_t offset)
{
return read32((void *)(ACPIMMIO_SMI_BASE + offset));
}
void smi_write8(uint8_t offset, uint8_t value)
{
write8((void *)(ACPIMMIO_SMI_BASE + offset), value);
}
void smi_write16(uint8_t offset, uint16_t value)
{
write16((void *)(ACPIMMIO_SMI_BASE + offset), value);
}
void smi_write32(uint8_t offset, uint32_t value)
{
write32((void *)(ACPIMMIO_SMI_BASE + offset), value);
}
/* pm read/write - access registers at 0xfed80300 */
u8 pm_read8(u8 reg)
{
return read8((void *)(ACPIMMIO_PMIO_BASE + reg));
}
void pm_write16(u8 reg, u16 value)
{
write16((void *)(ACPIMMIO_PMIO_BASE + reg), value);
}
u16 pm_read16(u8 reg)
{
return read16((void *)(ACPIMMIO_PMIO_BASE + reg));
}
void misc_write32(u8 reg, u32 value)
u32 pm_read32(u8 reg)
{
write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
return read32((void *)(ACPIMMIO_PMIO_BASE + reg));
}
u32 misc_read32(u8 reg)
void pm_write8(u8 reg, u8 value)
{
return read32((void *)(ACPIMMIO_MISC_BASE + reg));
write8((void *)(ACPIMMIO_PMIO_BASE + reg), value);
}
void pm_write16(u8 reg, u16 value)
{
write16((void *)(ACPIMMIO_PMIO_BASE + reg), value);
}
void pm_write32(u8 reg, u32 value)
@ -53,11 +84,59 @@ void pm_write32(u8 reg, u32 value)
write32((void *)(ACPIMMIO_PMIO_BASE + reg), value);
}
u32 pm_read32(u8 reg)
/* pm2 read/write - access registers at 0xfed80400 - currently unused */
/* biosram read/write - access registers at 0xfed80500 */
uint8_t biosram_read8(uint8_t offset)
{
return read32((void *)(ACPIMMIO_PMIO_BASE + reg));
return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset));
}
uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */
{
int i;
uint16_t value = 0;
for (i = sizeof(value) - 1 ; i >= 0 ; i--)
value = (value << 8) | biosram_read8(offset + i);
return value;
}
uint32_t biosram_read32(uint8_t offset)
{
uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16;
return value | biosram_read16(offset);
}
void biosram_write8(uint8_t offset, uint8_t value)
{
write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value);
}
void biosram_write16(uint8_t offset, uint16_t value)
{
int i;
for (i = 0 ; i < sizeof(value) ; i++) {
biosram_write8(offset + i, value & 0xff);
value >>= 8;
}
}
void biosram_write32(uint8_t offset, uint32_t value)
{
int i;
for (i = 0 ; i < sizeof(value) ; i++) {
biosram_write8(offset + i, value & 0xff);
value >>= 8;
}
}
/* cmosram read/write - access registers at 0xfed80600 - currently unused */
/* cmos read/write - access registers at 0xfed80700 - currently unused */
/* acpi read/write - access registers at 0xfed80800 */
u8 acpi_read8(u8 reg)
{
return read8((void *)(ACPIMMIO_ACPI_BASE + reg));
@ -88,119 +167,7 @@ void acpi_write32(u8 reg, u32 value)
write32((void *)(ACPIMMIO_ACPI_BASE + reg), value);
}
void smi_write32(uint8_t offset, uint32_t value)
{
write32((void *)(ACPIMMIO_SMI_BASE + offset), value);
}
uint32_t smi_read32(uint8_t offset)
{
return read32((void *)(ACPIMMIO_SMI_BASE + offset));
}
uint16_t smi_read16(uint8_t offset)
{
return read16((void *)(ACPIMMIO_SMI_BASE + offset));
}
void smi_write16(uint8_t offset, uint16_t value)
{
write16((void *)(ACPIMMIO_SMI_BASE + offset), value);
}
uint8_t smi_read8(uint8_t offset)
{
return read8((void *)(ACPIMMIO_SMI_BASE + offset));
}
void smi_write8(uint8_t offset, uint8_t value)
{
write8((void *)(ACPIMMIO_SMI_BASE + offset), value);
}
uint8_t biosram_read8(uint8_t offset)
{
return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset));
}
void biosram_write8(uint8_t offset, uint8_t value)
{
write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value);
}
/* BiosRam may only be accessed a byte at a time */
uint16_t biosram_read16(uint8_t offset)
{
int i;
uint16_t value = 0;
for (i = sizeof(value) - 1 ; i >= 0 ; i--)
value = (value << 8) | biosram_read8(offset + i);
return value;
}
uint32_t biosram_read32(uint8_t offset)
{
uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16;
return value | biosram_read16(offset);
}
void biosram_write16(uint8_t offset, uint16_t value)
{
int i;
for (i = 0 ; i < sizeof(value) ; i++) {
biosram_write8(offset + i, value & 0xff);
value >>= 8;
}
}
void biosram_write32(uint8_t offset, uint32_t value)
{
int i;
for (i = 0 ; i < sizeof(value) ; i++) {
biosram_write8(offset + i, value & 0xff);
value >>= 8;
}
}
uint16_t pm_acpi_pm_cnt_blk(void)
{
return pm_read16(PM1_CNT_BLK);
}
uint16_t pm_acpi_pm_evt_blk(void)
{
return pm_read16(PM_EVT_BLK);
}
void xhci_pm_write8(uint8_t reg, uint8_t value)
{
write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
}
uint8_t xhci_pm_read8(uint8_t reg)
{
return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg));
}
void xhci_pm_write16(uint8_t reg, uint16_t value)
{
write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
}
uint16_t xhci_pm_read16(uint8_t reg)
{
return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg));
}
void xhci_pm_write32(uint8_t reg, uint32_t value)
{
write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
}
uint32_t xhci_pm_read32(uint8_t reg)
{
return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg));
}
/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */
void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value)
{
@ -212,6 +179,76 @@ uint8_t smbus_read8(uint32_t mmio, uint8_t reg)
return read8((void *)(mmio + reg));
}
/* wdt read/write - access registers at 0xfed80b00 - not currently used */
/* hpet read/write - access registers at 0xfed80c00 - not currently used */
/* iomux read/write - access registers at 0xfed80d00 - not currently used */
/* misc read/write - access registers at 0xfed80e00 */
u32 misc_read32(u8 reg)
{
return read32((void *)(ACPIMMIO_MISC_BASE + reg));
}
void misc_write32(u8 reg, u32 value)
{
write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
}
/* dpvga read/write - access registers at 0xfed81400 - not currently used */
/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */
/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */
/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */
/* xhci_pm read/write - access registers at 0xfed81c00 */
uint8_t xhci_pm_read8(uint8_t reg)
{
return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg));
}
uint16_t xhci_pm_read16(uint8_t reg)
{
return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg));
}
uint32_t xhci_pm_read32(uint8_t reg)
{
return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg));
}
void xhci_pm_write8(uint8_t reg, uint8_t value)
{
write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
}
void xhci_pm_write16(uint8_t reg, uint16_t value)
{
write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
}
void xhci_pm_write32(uint8_t reg, uint32_t value)
{
write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
}
/* acdc_tmr read/write - access registers at 0xfed81d00 */
/* aoac read/write - access registers at 0xfed81e00 - not currently used */
uint16_t pm_acpi_pm_cnt_blk(void)
{
return pm_read16(PM1_CNT_BLK);
}
uint16_t pm_acpi_pm_evt_blk(void)
{
return pm_read16(PM_EVT_BLK);
}
int acpi_get_sleep_type(void)
{
return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk()));