intel/fsp_baytrail: Fix logging of ISPEnable option
Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP configuration option. TEST=Built and booted on Minnowboard Max Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/10126 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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@ -173,14 +173,14 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
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if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) {
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UpdData->ISPEnable = dev->enabled;
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} else {
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/* Gold2 and earlier FSP: ISPEnable is the filed */
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/* Gold2 and earlier FSP: ISPEnable is the field */
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/* next to PcdGttSize in UPD_DATA_REGION struct */
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*(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled;
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printk (FSP_INFO_LEVEL,
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"Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n");
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}
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printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n",
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UpdData->PcdEnableSdio?"Enabled":"Disabled");
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dev->enabled?"Enabled":"Disabled");
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break;
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case EMMC_DEV_FUNC: /* EMMC 4.1*/
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if ((dev->enabled) &&
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