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intel/fsp_baytrail: Fix logging of ISPEnable option 

Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP
configuration option.

TEST=Built and booted on Minnowboard Max

Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
David Imhoff 2015-05-06 21:42:37 +02:00 committed by Patrick Georgi
parent dfb53ef0a5
commit 6b0933adf7
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
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@ -173,14 +173,14 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) {
UpdData->ISPEnable = dev->enabled; UpdData->ISPEnable = dev->enabled;
} else { } else {
/* Gold2 and earlier FSP: ISPEnable is the filed */ /* Gold2 and earlier FSP: ISPEnable is the field */
/* next to PcdGttSize in UPD_DATA_REGION struct */ /* next to PcdGttSize in UPD_DATA_REGION struct */
*(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled;
printk (FSP_INFO_LEVEL, printk (FSP_INFO_LEVEL,
"Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n");
} }
printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n",
UpdData->PcdEnableSdio?"Enabled":"Disabled"); dev->enabled?"Enabled":"Disabled");
break; break;
case EMMC_DEV_FUNC: /* EMMC 4.1*/ case EMMC_DEV_FUNC: /* EMMC 4.1*/
if ((dev->enabled) && if ((dev->enabled) &&