sb/intel: Deduplicate vbnv_cmos_failed and rtc_init

* Move all implementations to into common folder.
* Add rtc.c for rtc based functions
Allows all Intel based platforms to use VBOOT_VBNV_CMOS.

Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/southbridge/intel/bd82x6x/early_pch_common.c

@@ -23,7 +23,6 @@
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <rules.h>
-#include <security/vboot/vbnv.h>
 
 #if ENV_ROMSTAGE
 uint64_t get_initial_timestamp(void)
@@ -62,18 +61,3 @@ int southbridge_detect_s3_resume(void)
 	return 0;
 }
 #endif
-
-int rtc_failure(void)
-{
-#if defined(__SIMPLE_DEVICE__)
-	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-#else
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
-	return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
-}
-
-int vbnv_cmos_failed(void)
-{
-	return rtc_failure();
-}

src/southbridge/intel/bd82x6x/lpc.c

@@ -27,7 +27,6 @@
 #include <arch/ioapic.h>
 #include <arch/acpi.h>
 #include <cpu/cpu.h>
-#include <elog.h>
 #include <arch/acpigen.h>
 #include <drivers/intel/gma/i915.h>
 #include <cpu/x86/smm.h>
@@ -39,6 +38,7 @@
 #include <southbridge/intel/common/pciehp.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <southbridge/intel/common/pmutil.h>
+#include <southbridge/intel/common/rtc.h>
 
 #define NMI_OFF	0
 
@@ -279,21 +279,6 @@ static void pch_power_options(struct device *dev)
 	RCBA32(0x3f02) = reg32;
 }
 
-static void pch_rtc_init(struct device *dev)
-{
-	int rtc_failed = rtc_failure();
-
-	if (rtc_failed) {
-		if (IS_ENABLED(CONFIG_ELOG))
-			elog_add_event(ELOG_TYPE_RTC_RESET);
-		pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0);
-	}
-
-	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
-
-	cmos_init(rtc_failed);
-}
-
 /* CougarPoint PCH Power Management init */
 static void cpt_pm_init(struct device *dev)
 {
@@ -605,7 +590,7 @@ static void lpc_init(struct device *dev)
 	//gpio_init(dev);
 
 	/* Initialize the real time clock. */
-	pch_rtc_init(dev);
+	sb_rtc_init();
 
 	/* Initialize ISA DMA. */
 	isa_dma_init();

src/southbridge/intel/bd82x6x/pch.h

@@ -100,9 +100,6 @@ void
 early_usb_init (const struct southbridge_usb_port *portmap);
 
 #endif
-
-/* Return non-zero when RTC failure happened. */
-int rtc_failure(void);
 #endif
 
 /* PM I/O Space */

src/southbridge/intel/common/Makefile.inc

@@ -54,4 +54,9 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c
 
 ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c
 
+romstage-y += rtc.c
+ramstage-y += rtc.c
+postcar-y += rtc.c
+smm-y += rtc.c
+
 endif

src/southbridge/intel/common/pmutil.h

@@ -21,6 +21,9 @@
 
 #define D31F0_PMBASE		0x40
 #define D31F0_GEN_PMCON_3	0xa4
+#define   RTC_BATTERY_DEAD		(1 << 2)
+#define   RTC_POWER_FAILED		(1 << 1)
+#define   SLEEP_AFTER_POWER_FAIL	(1 << 0)
 #define D31F0_GPIO_ROUT		0xb8
 #define  GPI_DISABLE		0x00
 #define  GPI_IS_SMI		0x01

src/southbridge/intel/common/rtc.c

@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <security/vboot/vbnv.h>
+#include <pc80/mc146818rtc.h>
+#include <elog.h>
+#include "pmutil.h"
+#include "rtc.h"
+
+/* PCI Configuration Space (D31:F0): LPC */
+#if defined(__SIMPLE_DEVICE__)
+#define PCH_LPC_DEV	PCI_DEV(0, 0x1f, 0)
+#else
+#define PCH_LPC_DEV	dev_find_slot(0, PCI_DEVFN(0x1f, 0))
+#endif
+
+int rtc_failure(void)
+{
+	return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3)
+		  & RTC_BATTERY_DEAD);
+}
+
+void sb_rtc_init(void)
+{
+	int rtc_failed = rtc_failure();
+
+	if (rtc_failed) {
+		if (IS_ENABLED(CONFIG_ELOG))
+			elog_add_event(ELOG_TYPE_RTC_RESET);
+		pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3,
+				   ~RTC_BATTERY_DEAD, 0);
+	}
+
+	printk(BIOS_DEBUG, "RTC: failed = 0x%x\n", rtc_failed);
+
+	cmos_init(rtc_failed);
+}
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failure();
+}

src/southbridge/intel/common/rtc.h

@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_RTC_H
+#define SOUTHBRIDGE_INTEL_RTC_H
+
+/* Return non-zero when RTC failure happened. */
+int rtc_failure(void);
+void sb_rtc_init(void);
+
+#endif

src/southbridge/intel/lynxpoint/lpc.c

@@ -28,7 +28,6 @@
 #include <arch/acpi.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/smm.h>
-#include <elog.h>
 #include <cbmem.h>
 #include <string.h>
 #include "nvs.h"
@@ -37,6 +36,7 @@
 #include <cbmem.h>
 #include <drivers/intel/gma/i915.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
+#include <southbridge/intel/common/rtc.h>
 
 #define NMI_OFF	0
 
@@ -288,21 +288,6 @@ static void pch_power_options(struct device *dev)
 	RCBA16(0x3f02) = reg16;
 }
 
-static void pch_rtc_init(struct device *dev)
-{
-	int rtc_failed = rtc_failure();
-
-	if (rtc_failed) {
-		if (IS_ENABLED(CONFIG_ELOG))
-			elog_add_event(ELOG_TYPE_RTC_RESET);
-		pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0);
-	}
-
-	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
-
-	cmos_init(rtc_failed);
-}
-
 /* LynxPoint PCH Power Management init */
 static void lpt_pm_init(struct device *dev)
 {
@@ -576,7 +561,7 @@ static void lpc_init(struct device *dev)
 	}
 
 	/* Initialize the real time clock. */
-	pch_rtc_init(dev);
+	sb_rtc_init();
 
 	/* Initialize ISA DMA. */
 	isa_dma_init();

src/southbridge/intel/lynxpoint/pch.h

@@ -172,9 +172,6 @@ void disable_all_gpe(void);
 void enable_gpe(u32 mask);
 void disable_gpe(u32 mask);
 
-/* Return non-zero when RTC failure happened. */
-int rtc_failure(void);
-
 #if !defined(__PRE_RAM__) && !defined(__SMM__)
 #include <device/device.h>
 #include <arch/acpi.h>

src/southbridge/intel/lynxpoint/pmutil.c

@@ -24,7 +24,6 @@
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <console/console.h>
-#include <security/vboot/vbnv.h>
 #include "pch.h"
 
 #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
@@ -554,18 +553,3 @@ void disable_gpe(u32 mask)
 	gpe0_en &= ~mask;
 	outl(gpe0_en, get_pmbase() + gpe0_reg);
 }
-
-int rtc_failure(void)
-{
-#if defined(__SIMPLE_DEVICE__)
-	pci_devfn_t dev = PCI_DEV(0, 31, 0);
-#else
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0));
-#endif
-	return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
-}
-
-int vbnv_cmos_failed(void)
-{
-	return rtc_failure();
-}