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Improving BKDG implementation of P-states, 

CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Xavi Drudis Ferran 2011-02-28 03:56:52 +00:00 committed by Marc Jones
parent 061c89e15d
commit 6bdc83bf5e
3 changed files with 3 additions and 5 deletions
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2
src/cpu/amd/model_10xxx/fidvid.c
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@ -738,7 +738,7 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid)
} }
static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
{ {
u32 send; u32 send;

5
src/cpu/amd/model_10xxx/init_cpus.c
View File

@ -157,7 +157,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
} }
#if CONFIG_SET_FIDVID #if CONFIG_SET_FIDVID
static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid); static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
#endif #endif
static inline __attribute__ ((always_inline)) static inline __attribute__ ((always_inline))
@ -346,8 +346,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"init_fidvid_ap(stage1) apicid: %02x\n", "init_fidvid_ap(stage1) apicid: %02x\n",
apicid); apicid);
init_fidvid_ap(bsp_apicid, apicid, id.nodeid, init_fidvid_ap(apicid, id.nodeid, id.coreid);
id.coreid);
} }
} }
#endif #endif

1
src/northbridge/amd/amdht/AsPsDefs.h
View File

@ -58,7 +58,6 @@
#define PS_NB_VID_SHFT 25 /* P-state bit shift for NbVid */ #define PS_NB_VID_SHFT 25 /* P-state bit shift for NbVid */
#define PS_BOTH_VID_OFF 0x01ff01ff /* Mask NbVid & CpuVid */ #define PS_BOTH_VID_OFF 0x01ff01ff /* Mask NbVid & CpuVid */
#define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */ #define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */
#define PS_NB_VID_SHFT 25 /* P-state NBVID shift */
#define PS_DIS 0x7fffffff /* disable P-state reg */ #define PS_DIS 0x7fffffff /* disable P-state reg */
#define PS_EN 0x80000000 /* enable P-state reg */ #define PS_EN 0x80000000 /* enable P-state reg */
#define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid] #define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid]