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intel/i945 boards: Add romstage time stamps 

Currently, some Intel 945 boards miss some or all of the time stamps
*1:start of rom stage*, *2:before ram initialization*, and *3:after ram
initialization*, so add them.

Use the same formatting as used for the board Lenovo X60, which already
has code for all the time stamps.

Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Paul Menzel 2016-12-29 22:54:02 +01:00 committed by Kyösti Mälkki
parent 68fdb785b2
commit 6c20b65849
7 changed files with 44 additions and 0 deletions
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7
src/mainboard/asus/p5gc-mx/romstage.c
View File

@ -26,6 +26,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <timestamp.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <pc80/mc146818rtc.h>
@ -216,6 +217,9 @@ void mainboard_romstage_entry(unsigned long bist)
u8 m_bsel;
u8 c_bsel = msr_get_fsb();
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
@ -252,7 +256,10 @@ void mainboard_romstage_entry(unsigned long bist)
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();

2
src/mainboard/getac/p470/romstage.c
View File

@ -306,7 +306,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, NULL);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();

8
src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
View File

@ -25,6 +25,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <timestamp.h>
#include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h>
#include <pc80/mc146818rtc.h>
@ -165,6 +166,10 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0, boot_mode = 0;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
@ -200,7 +205,10 @@ void mainboard_romstage_entry(unsigned long bist)
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();

6
src/mainboard/ibase/mb899/romstage.c
View File

@ -24,6 +24,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <timestamp.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <pc80/mc146818rtc.h>
@ -222,6 +223,9 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
@ -254,7 +258,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, NULL);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();

7
src/mainboard/intel/d945gclf/romstage.c
View File

@ -24,6 +24,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <timestamp.h>
#include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
@ -154,6 +155,10 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0, boot_mode = 0;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
@ -187,7 +192,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();

7
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -20,6 +20,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <timestamp.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
@ -324,6 +325,10 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
@ -361,7 +366,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, NULL);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();

7
src/mainboard/roda/rk886ex/romstage.c
View File

@ -25,6 +25,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <timestamp.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
@ -245,6 +246,10 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
@ -285,7 +290,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, NULL);
timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();