soc/intel/tigerlake: Implement function to map physical port to EC port

Currently coreboot and EC had different logic to interpret TCSS port
number which would break retimer update functionality since coreboot
would pass wrong port information to EC.

This change clones the implementation on Alder Lake which converts
the phyiscal port mapping to EC's abstract port mapping.

BUG=b:207057940
BRANCH=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/tigerlake/Makefile.inc

@@ -37,6 +37,7 @@ ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
+ramstage-y += retimer.c
 ramstage-y += soundwire.c
 ramstage-y += systemagent.c
 ramstage-y += xhci.c

src/soc/intel/tigerlake/retimer.c

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <drivers/intel/usb4/retimer/retimer.h>
+#include <intelblocks/tcss.h>
+
+int retimer_get_index_for_typec(uint8_t typec_port)
+{
+	int ec_port = 0;
+
+	const struct device *tcss_port_arr[] = {
+		DEV_PTR(tcss_usb3_port1),
+		DEV_PTR(tcss_usb3_port2),
+		DEV_PTR(tcss_usb3_port3),
+		DEV_PTR(tcss_usb3_port4),
+	};
+
+	for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) {
+		if (i == typec_port) {
+			printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", typec_port,
+					ec_port);
+			return ec_port;
+		}
+
+		if (is_dev_enabled(tcss_port_arr[i]))
+			ec_port++;
+	}
+
+	// Code should not come here if typec_port input is correct
+	return -1;
+}