AMD fam10: Drop MEM_TRAIN_SEQ

This config was for AMD K8 only.

Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4555
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/mainboard/advansus/a785e-i/Kconfig

@@ -56,10 +56,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/amd/bimini_fam10/Kconfig

@@ -56,10 +56,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/amd/mahogany_fam10/Kconfig

@@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/amd/serengeti_cheetah_fam10/Kconfig

@@ -45,10 +45,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 8
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2

src/mainboard/amd/tilapia_fam10/Kconfig

@@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/asus/m4a78-em/Kconfig

@@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/asus/m4a785-m/Kconfig

@@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/asus/m4a785t-m/Kconfig

@@ -46,10 +46,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/asus/m5a88-v/Kconfig

@@ -54,10 +54,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/avalue/eax-785e/Kconfig

@@ -56,10 +56,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/gigabyte/ma785gm/Kconfig

@@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/gigabyte/ma785gmt/Kconfig

@@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/gigabyte/ma78gm/Kconfig

@@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/iei/kino-780am2-fam10/Kconfig

@@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/jetway/pa78vm5/Kconfig

@@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 2
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/msi/ms9652_fam10/Kconfig

@@ -133,10 +133,6 @@ config RAMTOP
 	hex
 	default 0x1000000
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config AMD_UCODE_PATCH_FILE
 	string
 	default "mc_patch_01000096.h"

src/mainboard/supermicro/h8dmr_fam10/Kconfig

@@ -49,10 +49,6 @@ config APIC_ID_OFFSET
 	hex
 	default 0x0
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2

src/mainboard/supermicro/h8qme_fam10/Kconfig

@@ -48,10 +48,6 @@ config APIC_ID_OFFSET
 	hex
 	default 0x0
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2

src/mainboard/supermicro/h8scm_fam10/Kconfig

@@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 1
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

src/mainboard/tyan/s2912_fam10/Kconfig

@@ -37,10 +37,6 @@ config APIC_ID_OFFSET
 	hex
 	default 0
 
-config MEM_TRAIN_SEQ
-	int
-	default 2
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2

src/northbridge/amd/amdfam10/Kconfig

@@ -38,10 +38,6 @@ config AMDMCT
 	bool
 	default y
 
-config MEM_TRAIN_SEQ
-	int
-	default 0
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000

src/northbridge/amd/amdfam10/amdfam10.h

@@ -1038,13 +1038,7 @@ struct nodes_info_t {
 
 //#define MEM_CS_COPY 1
 #define MEM_CS_COPY NODE_NUMS
-
+#define DQS_DELAY_COPY NODE_NUMS
-#if CONFIG_MEM_TRAIN_SEQ == 0
-	#define DQS_DELAY_COPY NODE_NUMS
-#else
-//	#define DQS_DELAY_COPY 1
-	#define DQS_DELAY_COPY NODE_NUMS
-#endif
 #endif