first round of agami aruma merge
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -177,7 +177,7 @@ chip northbridge/amd/amdk8/root_complex
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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device pnp 2e.3 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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@ -74,9 +74,9 @@ default FALLBACK_SIZE=0x40000
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default HAVE_FALLBACK_BOOT=1
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##
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## incoherent_ht.c does all the work. we don't want hard reset.
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## Use hard_reset for rebooting, it uses reg. 0xcf9 in the amd8111.
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##
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default HAVE_HARD_RESET=0
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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@ -205,6 +205,8 @@ default TTYS0_LCS=0x3
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## These values can be overwritten by LinuxBIOSv2/targets/agami/aruma/Config.lb
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=8
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## At a maximum only compile in this level of debugging
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@ -16,7 +16,7 @@ extern unsigned char AmlCode[];
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unsigned long acpi_dump_apics(unsigned long current)
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{
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unsigned int gsi_base=0x18, ioapic_nr=2;
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unsigned int gsi_base=0x18, ioapic_nr=2, i;
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device_t dev=0;
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/* create all subtables for 4p */
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@ -29,6 +29,30 @@ unsigned long acpi_dump_apics(unsigned long current)
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 1,
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IO_APIC_ADDR, 0);
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/* Write the two onboard 8131 IOAPICs */
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for(i = 0; i < 2; i++) {
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if (dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev)){
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ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr);
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ioapic_nr++;
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}
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}
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/* The doughter card may contain either 8131 or 8132 */
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/* Write the 8132 IOAPICs if they exist */
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for(i = 0; i < 4; i++) {
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if (dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7459, dev)){
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ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr);
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ioapic_nr++;
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}
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}
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/* In the event there were no 8132s look for the 8131s
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* but skip the two onboard 8131
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*/
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dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, 0);
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dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev);
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/* Write all 8131 IOAPICs */
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while((dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev))) {
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ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr);
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@ -83,6 +107,7 @@ void acpi_create_lnxb(acpi_lnxb_t *lnxb)
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/* first skip the onboard 8131 */
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dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, 0);
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dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, dev);
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/* now look at the last 8131 in each chain,
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* as it contains the valid bus ranges
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*/
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@ -32,8 +32,9 @@
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static void hard_reset(void)
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{
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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outb(0x0e, 0x0cf9);
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// pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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// outb(0x0e, 0x0cf9);
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outb(0x06, 0x0cf9); /* this value will assert RESET_L and LDTRST_L */
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}
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static void soft_reset(void)
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@ -71,7 +71,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
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fadt->reset_reg.addrl = 0xcf9;
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fadt->reset_reg.addrh = 0x0;
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fadt->reset_value = 6;
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fadt->reset_value = 0x06;
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fadt->x_firmware_ctl_l = facs;
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = dsdt;
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@ -97,6 +97,16 @@ static void acpi_init(struct device *dev)
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#endif
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/* To enable the register 0xcf9 in the IO space
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* bit [D5] is set in the amd8111 configuration register.
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* The config. reg. is devBx41. Register 0xcf9 allows
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* hard reset capability to the system. For the ACPI
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* reset.reg values in fadt.c to work this register
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* must be enabled.
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*/
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byte = pci_read_config8(dev, 0x41);
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pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
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/* power on after power fail */
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on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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get_option(&on, "power_on_after_fail");
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