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cpu/intel/msr.h: Sort MSRs in ascending order 

Sort MSR definitions in ascending order to keep things organized.

Change-Id: Iadfd28014dc6f41dae7b52b1550c699c89fe8bdc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Angel Pons 2021-06-13 11:24:11 +02:00 committed by Patrick Georgi
parent d1fca8f7f7
commit 6ccb252918
1 changed files with 4 additions and 4 deletions
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8
src/include/cpu/intel/msr.h
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@ -7,10 +7,6 @@
* Common MSRs for Intel CPUs * Common MSRs for Intel CPUs
*/ */
#define MSR_FEATURE_CONFIG 0x13c
#define AESNI_DISABLE (1 << 1)
#define AESNI_LOCK (1 << 0)
#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PIC_MSG_CONTROL 0x2e
#define TPR_UPDATES_DISABLE (1 << 10) #define TPR_UPDATES_DISABLE (1 << 10)
@ -26,6 +22,10 @@
#define B_BOOT_GUARD_SACM_INFO_BTG_CAPABILITY (1ull << 32) #define B_BOOT_GUARD_SACM_INFO_BTG_CAPABILITY (1ull << 32)
#define B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY (1ull << 34) #define B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY (1ull << 34)
#define MSR_FEATURE_CONFIG 0x13c
#define AESNI_DISABLE (1 << 1)
#define AESNI_LOCK (1 << 0)
#define MSR_PKG_C10_RESIDENCY 0x632 #define MSR_PKG_C10_RESIDENCY 0x632
#endif /* CPU_INTEL_MSR_H */ #endif /* CPU_INTEL_MSR_H */