cpu/intel/msr.h: Sort MSRs in ascending order
Sort MSR definitions in ascending order to keep things organized. Change-Id: Iadfd28014dc6f41dae7b52b1550c699c89fe8bdc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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@ -7,10 +7,6 @@
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* Common MSRs for Intel CPUs
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*/
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#define MSR_FEATURE_CONFIG 0x13c
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#define AESNI_DISABLE (1 << 1)
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#define AESNI_LOCK (1 << 0)
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define TPR_UPDATES_DISABLE (1 << 10)
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@ -26,6 +22,10 @@
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#define B_BOOT_GUARD_SACM_INFO_BTG_CAPABILITY (1ull << 32)
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#define B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY (1ull << 34)
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#define MSR_FEATURE_CONFIG 0x13c
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#define AESNI_DISABLE (1 << 1)
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#define AESNI_LOCK (1 << 0)
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#define MSR_PKG_C10_RESIDENCY 0x632
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#endif /* CPU_INTEL_MSR_H */
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