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soc/intel/baytrail,braswell: Drop aliases on MMCONF_BASE_ADDRESS 

Add MMCONF_BUS_NUMBER=256 to match previous allocation.

Change-Id: I01a86481e392a9347afdc2860b58617b20c4f05a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-02-14 01:55:18 +02:00 committed by Patrick Georgi
parent c4b3903361
commit 6d085446fe
8 changed files with 14 additions and 14 deletions
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4
src/soc/intel/baytrail/Kconfig
View File

@ -44,6 +44,10 @@ config VBOOT
config MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
int
default 256
config MAX_CPUS
int
default 4

2
src/soc/intel/baytrail/acpi.c
View File

@ -97,7 +97,7 @@ int acpi_sci_irq(void)
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
MCFG_BASE_ADDRESS, 0, 0, 255);
CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}

4
src/soc/intel/baytrail/acpi/southcluster.asl
View File

@ -198,7 +198,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
@ -247,7 +247,7 @@ Device (IOSF)
Method (_CRS)
{
CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS)
Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
Return (^RBUF)
}
}

4
src/soc/intel/baytrail/include/soc/iomap.h
View File

@ -7,10 +7,6 @@
* Memory Mapped IO bases.
*/
/* PCI Configuration Space */
#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define MCFG_BASE_SIZE 0x10000000
/* Transactions in this range will abort */
#define ABORT_BASE_ADDRESS 0xfeb00000
#define ABORT_BASE_SIZE 0x00100000

4
src/soc/intel/braswell/Kconfig
View File

@ -59,6 +59,10 @@ config VBOOT
config MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
int
default 256
config MAX_CPUS
int
default 4

2
src/soc/intel/braswell/acpi.c
View File

@ -107,7 +107,7 @@ int acpi_sci_irq(void)
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
MCFG_BASE_ADDRESS, 0, 0, 255);
CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}

4
src/soc/intel/braswell/acpi/southcluster.asl
View File

@ -197,7 +197,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
@ -246,7 +246,7 @@ Device (IOSF)
Method (_CRS)
{
CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS)
Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
Return (^RBUF)
}
}

4
src/soc/intel/braswell/include/soc/iomap.h
View File

@ -7,10 +7,6 @@
* Memory Mapped IO bases.
*/
/* PCI Configuration Space */
#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define MCFG_BASE_SIZE 0x10000000
/* Transactions in this range will abort */
#define ABORT_BASE_ADDRESS 0xfeb00000
#define ABORT_BASE_SIZE 0x00100000