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mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/B 

During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is
copied to CSE_RW, so the sizes of these regions need to match.

BUG=b:189177538
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Reka Norman 2021-11-08 14:53:19 +11:00 committed by Tim Wawrzynczak
parent ba2b1139f1
commit 6d27905e03
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/intel/adlrvp/chromeos.fmd
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@ -15,7 +15,7 @@ FLASH 32M {
VBLOCK_A 64K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 4032K
ME_RW_A(CBFS) 3520K
}
RW_LEGACY(CBFS) 1M
RW_MISC 1M {
@ -39,7 +39,7 @@ FLASH 32M {
VBLOCK_B 64K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 4032K
ME_RW_B(CBFS) 3520K
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.