mb/google/hatch: Enable H1 TPM support over SPI interface
Add code support to enable H1 TPM interfaced to SOC on GSPI0. The TPM interrupt is mapped to GPP_C21. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30210 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra
Subrata Banik
parent
368598198d
commit
6d8e0cdeab
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@ -10,14 +10,13 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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select MAINBOARD_HAS_SPI_TPM_CR50
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select MAINBOARD_HAS_TPM2
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select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
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select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
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select SOC_INTEL_COFFEELAKE
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM2
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if BOARD_GOOGLE_BASEBOARD_HATCH
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@ -29,6 +28,10 @@ config CHROMEOS
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select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config DIMM_MAX
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int
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default 2
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@ -37,6 +40,9 @@ config DIMM_SPD_SIZE
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int
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default 512
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config DRIVER_TPM_SPI_BUS
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default 0x1
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config GBB_HWID
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string
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depends on CHROMEOS
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@ -62,18 +68,18 @@ config MAX_CPUS
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int
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default 8
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config VARIANT_DIR
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string
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default "hatch" if BOARD_GOOGLE_HATCH
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 53 # GPE0_DW1_21 (GPP_C21)
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config VARIANT_DIR
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string
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default "hatch" if BOARD_GOOGLE_HATCH
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config VBOOT
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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@ -1,4 +1,31 @@
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chip soc/intel/cannonlake
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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# DW1 is used by:
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# - GPP_C21 - H1_PCH_INT_ODL
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register "gpe0_dw0" = "PMC_GPP_A"
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register "gpe0_dw1" = "PMC_GPP_C"
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register "gpe0_dw2" = "PMC_GPP_D"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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}"
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device domain 0 on
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device pci 00.0 off end # Host Bridge
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device pci 02.0 off end # Integrated Graphics Device
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@ -39,7 +66,14 @@ chip soc/intel/cannonlake
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device pci 1d.4 off end # PCI Express Port 13 (x4)
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.2 on
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chip drivers/spi/acpi
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "compat_string" = ""google,cr50""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
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device spi 0 on end
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end
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end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 off end # LPC/eSPI
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device pci 1f.1 off end # P2SB
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@ -19,6 +19,16 @@
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#include <commonlib/helpers.h>
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static const struct pad_config gpio_table[] = {
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/* H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
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};
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const struct pad_config *__weak variant_gpio_table(size_t *num)
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@ -29,6 +39,16 @@ const struct pad_config *__weak variant_gpio_table(size_t *num)
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/* GPIOs needed prior to ramstage. */
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static const struct pad_config early_gpio_table[] = {
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/* H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
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};
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const struct pad_config *__weak variant_early_gpio_table(size_t *num)
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