soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKE
Intel Apollolake does not support the bootguard MSRs 0x139 MSR_BC_PBEC and 0x13A MSR_BOOT_GUARD_SACM_INFO. Change-Id: Ief40028a1c85084e012a83db8080d478e407487b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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@ -96,6 +96,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_CSE
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select SOC_INTEL_COMMON_BLOCK_CSE
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select SOC_INTEL_COMMON_BLOCK_SMBUS
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select SOC_INTEL_COMMON_BLOCK_SMBUS
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_NO_BOOTGUARD_MSR
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select UDELAY_TSC
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select UDELAY_TSC
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select TSC_MONOTONIC_TIMER
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select TSC_MONOTONIC_TIMER
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@ -107,3 +107,9 @@ config CPU_SUPPORTS_PM_TIMER_EMULATION
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Select this if the SoC's ucode supports PM ACPI timer emulation (Common
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Select this if the SoC's ucode supports PM ACPI timer emulation (Common
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timer Copy), which is required to be able to disable the TCO PM ACPI
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timer Copy), which is required to be able to disable the TCO PM ACPI
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timer for power saving.
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timer for power saving.
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config SOC_INTEL_NO_BOOTGUARD_MSR
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bool
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help
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Select this on platforms that do not support Bootguard related MSRs
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0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO.
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@ -66,9 +66,13 @@
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* Returns %eax and sets/unsets zero flag
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* Returns %eax and sets/unsets zero flag
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*/
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*/
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.macro is_bootguard_nem
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.macro is_bootguard_nem
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#if CONFIG(SOC_INTEL_NO_BOOTGUARD_MSR)
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xorl %eax, %eax
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#else
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movl $MSR_BOOT_GUARD_SACM_INFO, %ecx
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movl $MSR_BOOT_GUARD_SACM_INFO, %ecx
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rdmsr
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rdmsr
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andl $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax
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andl $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax
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#endif
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.endm
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.endm
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.global bootblock_pre_c_entry
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.global bootblock_pre_c_entry
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