soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKE

Intel Apollolake does not support the bootguard MSRs 0x139 MSR_BC_PBEC
and 0x13A MSR_BOOT_GUARD_SACM_INFO.

Change-Id: Ief40028a1c85084e012a83db8080d478e407487b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/soc/intel/apollolake/Kconfig

@@ -96,6 +96,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_CSE
 	select SOC_INTEL_COMMON_BLOCK_SMBUS
 	select SOC_INTEL_COMMON_FSP_RESET
+	select SOC_INTEL_NO_BOOTGUARD_MSR
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER

src/soc/intel/common/block/cpu/Kconfig

@@ -107,3 +107,9 @@ config CPU_SUPPORTS_PM_TIMER_EMULATION
 	  Select this if the SoC's ucode supports PM ACPI timer emulation (Common
 	  timer Copy), which is required to be able to disable the TCO PM ACPI
 	  timer for power saving.
+
+config SOC_INTEL_NO_BOOTGUARD_MSR
+	bool
+	help
+	  Select this on platforms that do not support Bootguard related MSRs
+	  0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO.

src/soc/intel/common/block/cpu/car/cache_as_ram.S

@@ -66,9 +66,13 @@
  * Returns %eax and sets/unsets zero flag
  */
 .macro is_bootguard_nem
+#if CONFIG(SOC_INTEL_NO_BOOTGUARD_MSR)
+	xorl	%eax, %eax
+#else
 	movl	$MSR_BOOT_GUARD_SACM_INFO, %ecx
 	rdmsr
 	andl	$B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax
+#endif
 .endm
 
 .global bootblock_pre_c_entry