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Revert "include/cpu/x86: Add STM Support" 

This reverts commit 297b6b862a.

Reason for revert: breaks smm. No code is using these fields. Original patch incomplete.

Change-Id: I6acf15dc9d77ed8a83b98f086f2a0b306c584a9b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37096
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aaron Durbin 2019-12-18 15:44:40 +00:00 committed by Matt DeVillier
parent 1a8dbfc899
commit 6dc2fda469
2 changed files with 0 additions and 9 deletions
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6
src/include/cpu/x86/msr.h
View File

@ -30,10 +30,6 @@
#define IA32_BIOS_SIGN_ID 0x8b
#define IA32_MPERF 0xe7
#define IA32_APERF 0xe8
/* STM */
#define IA32_SMM_MONITOR_CTL_MSR 0x9B
#define SMBASE_RO_MSR 0x98
#define IA32_SMM_MONITOR_VALID (1<<0)
#define IA32_MCG_CAP 0x179
#define MCG_CTL_P (1 << 3)
#define MCA_BANKS_MASK 0xff
@ -52,8 +48,6 @@
#define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401
#define IA32_VMX_BASIC_MSR 0x480
#define IA32_VMX_MISC_MSR 0x485
#define MCA_STATUS_HI_VAL (1UL << (63 - 32))
#define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
#define MCA_STATUS_HI_UC (1UL << (61 - 32))

3
src/include/cpu/x86/smm.h
View File

@ -64,9 +64,6 @@ extern unsigned char _binary_smm_end[];
struct smm_runtime {
u32 smbase;
u32 save_state_size;
u32 num_cpus;
/* STM's 32bit entry into SMI handler */
u32 start32_offset;
/* The apic_id_to_cpu provides a mapping from APIC id to CPU number.
* The CPU number is indicated by the index into the array by matching
* the default APIC id and value at the index. The stub loader