mb/google/rex: Add MPTS method for WWAN over PCIe
This patch generates the following for the mainboard: Scope (\_SB) { Method (MPTS, 1, Serialized) { Local0 = \_SB.PCI0.RP06.RTD3._STA () If ((Local0 == One)) { \_SB.PCI0.RP06.PXSX.DPTS (Arg0) } } } Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70229 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1,12 +1,16 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <drivers/wwan/fm/chip.h>
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#include <ec/ec.h>
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#include <ec/ec.h>
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#include <fw_config.h>
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#include <fw_config.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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WEAK_DEV_PTR(rp6_wwan);
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static void mainboard_init(void *chip_info)
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static void mainboard_init(void *chip_info)
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{
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{
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const struct pad_config *pads;
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const struct pad_config *pads;
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@ -15,9 +19,37 @@ static void mainboard_init(void *chip_info)
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gpio_configure_pads(pads, num);
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gpio_configure_pads(pads, num);
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}
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}
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static void mainboard_generate_wwan_shutdown(const struct device *dev)
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{
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const struct drivers_wwan_fm_config *config = config_of(dev);
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const struct device *parent = dev->bus->dev;
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if (!config)
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return;
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if (config->rtd3dev) {
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acpigen_write_store();
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acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA"));
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acpigen_emit_byte(LOCAL0_OP);
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acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP);
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{
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acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS"));
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acpigen_emit_byte(ARG0_OP);
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}
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acpigen_write_if_end();
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}
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}
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static void mainboard_fill_ssdt(const struct device *dev)
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static void mainboard_fill_ssdt(const struct device *dev)
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{
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{
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/* TODO: Add mainboard-specific SSDT entries */
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const struct device *wwan = DEV_PTR(rp6_wwan);
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if (wwan) {
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acpigen_write_scope("\\_SB");
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acpigen_write_method_serialized("MPTS", 1);
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mainboard_generate_wwan_shutdown(wwan);
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acpigen_write_method_end(); /* Method */
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acpigen_write_scope_end(); /* Scope */
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}
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}
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}
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static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
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static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
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@ -450,7 +450,9 @@ chip soc/intel/meteorlake
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register "srcclk_pin" = "3"
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register "srcclk_pin" = "3"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "skip_on_off_support" = "true"
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register "skip_on_off_support" = "true"
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device generic 0 alias rp6_rtd3 on end
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device generic 0 alias rp6_rtd3 on
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probe CELLULAR CELLULAR_PCIE
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end
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end
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end
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chip drivers/wwan/fm
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chip drivers/wwan/fm
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register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)"
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register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)"
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@ -459,7 +461,9 @@ chip soc/intel/meteorlake
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
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register "add_acpi_dma_property" = "true"
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register "add_acpi_dma_property" = "true"
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use rp6_rtd3 as rtd3dev
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use rp6_rtd3 as rtd3dev
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device generic 0 on end
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device generic 0 alias rp6_wwan on
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probe CELLULAR CELLULAR_PCIE
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end
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end
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end
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end #PCIE6 WWAN card
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end #PCIE6 WWAN card
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device ref pcie_rp7 on
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device ref pcie_rp7 on
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