soc/intel/broadwell: Fix other issues detected by checkpatch

Fix the following error and warnings detected by checkpatch.pl:

ERROR: switch and case should be at the same indent
WARNING: line over 80 characters
WARNING: storage class should be at the beginning of the declaration
WARNING: adding a line without newline at end of file
WARNING: __func__ should be used instead of gcc specific __FUNCTION__
WARNING: Comparisons should place the constant on the right side of the test

TEST=None

Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18885
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/broadwell/include/soc/igd.h

@@ -17,4 +17,4 @@
 u32 igd_get_reg_em4(void);
 u32 igd_get_reg_em5(void);
 
-#endif /* SOC_INTEL_BROADWELL_GMA_H */
+#endif /* SOC_INTEL_BROADWELL_GMA_H */

src/soc/intel/broadwell/include/soc/romstage.h

@@ -29,9 +29,9 @@ struct romstage_params {
 
 void mainboard_romstage_entry(struct romstage_params *params);
 void romstage_common(struct romstage_params *params);
-void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,
+asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_lo,
 			       uint32_t tsc_high);
-void asmlinkage romstage_after_car(void);
+asmlinkage void romstage_after_car(void);
 void raminit(struct pei_data *pei_data);
 void *setup_stack_and_mttrs(void);
 

src/soc/intel/broadwell/lpc.c

@@ -478,7 +478,7 @@ static void pch_lpc_add_mmio_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	/* RCBA */
-	if (RCBA_BASE_ADDRESS < default_decode_base) {
+	if (default_decode_base > RCBA_BASE_ADDRESS) {
 		res = new_resource(dev, RCBA);
 		res->base = RCBA_BASE_ADDRESS;
 		res->size = 16 * 1024;

src/soc/intel/broadwell/me.c

@@ -698,7 +698,7 @@ static me_bios_path intel_me_path(device_t dev)
 	/* Check if the MBP is ready */
 	if (!hfs2.mbp_rdy) {
 		printk(BIOS_CRIT, "%s: mbp is not ready!\n",
-		       __FUNCTION__);
+		       __func__);
 		path = ME_ERROR_BIOS_PATH;
 	}
 

src/soc/intel/broadwell/pcie.c

@@ -266,7 +266,8 @@ static void pcie_enable_clock_gating(void)
 			 * In addition to D28Fx PCICFG 420h[30:29] = 11b,
 			 * set 420h[17] = 0b and 420[0] = 1b for L1 SubState.
 			 */
-			pci_update_config32(dev, 0x420, ~0x20000, (3 << 29) | 1);
+			pci_update_config32(dev, 0x420, ~0x20000,
+				(3 << 29) | 1);
 
 		/* Configure shared resource clock gating. */
 		if (rp == 1 || rp == 5 || rp == 6)
@@ -385,29 +386,29 @@ static void root_port_check_disable(device_t dev)
 
 	/* Check Root Port Configuration. */
 	switch (rp) {
-		case 2:
+	case 2:
-			/* Root Port 2 is disabled for all lane configurations
+		/* Root Port 2 is disabled for all lane configurations
-			 * but config 00b (4x1 links). */
+		 * but config 00b (4x1 links). */
-			if ((rpc.strpfusecfg1 >> 14) & 0x3) {
+		if ((rpc.strpfusecfg1 >> 14) & 0x3) {
-				root_port_mark_disable(dev);
+			root_port_mark_disable(dev);
-				return;
+			return;
-			}
+		}
-			break;
+		break;
-		case 3:
+	case 3:
-			/* Root Port 3 is disabled in config 11b (1x4 links). */
+		/* Root Port 3 is disabled in config 11b (1x4 links). */
-			if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) {
+		if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) {
-				root_port_mark_disable(dev);
+			root_port_mark_disable(dev);
-				return;
+			return;
-			}
+		}
-			break;
+		break;
-		case 4:
+	case 4:
-			/* Root Port 4 is disabled in configs 11b (1x4 links)
+		/* Root Port 4 is disabled in configs 11b (1x4 links)
-			 * and 10b (2x2 links). */
+		 * and 10b (2x2 links). */
-			if ((rpc.strpfusecfg1 >> 14) & 0x2) {
+		if ((rpc.strpfusecfg1 >> 14) & 0x2) {
-				root_port_mark_disable(dev);
+			root_port_mark_disable(dev);
-				return;
+			return;
-			}
+		}
-			break;
+		break;
 	}
 
 	/* Check Pin Ownership. */
@@ -487,7 +488,8 @@ static void pch_pcie_early(struct device *dev)
 
 	if (do_aspm) {
 		/* Set ASPM bits in MPC2 register. */
-		pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
+		pci_update_config32(dev, 0xd4, ~(0x3 << 2),
+			(1 << 4) | (0x2 << 2));
 
 		/* Set unique clock exit latency in MPC register. */
 		pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
@@ -552,7 +554,8 @@ static void pch_pcie_early(struct device *dev)
 	pci_update_config8(dev, 0xf5, 0x0f, 0);
 
 	/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
-	pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
+	pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+		(1 << 29) | 0x10001);
 
 	/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
 	pci_update_config32(dev, 0x200, ~0xffff, 0x001e);

src/soc/intel/broadwell/romstage/romstage.c

@@ -119,7 +119,7 @@ void romstage_common(struct romstage_params *params)
 #endif
 }
 
-void asmlinkage romstage_after_car(void)
+asmlinkage void romstage_after_car(void)
 {
 	/* Load the ramstage. */
 	run_ramstage();

src/soc/intel/broadwell/smihandler.c

@@ -118,7 +118,8 @@ static void backlight_off(void)
 	uint32_t pp_ctrl;
 	uint32_t bl_off_delay;
 
-	reg_base = (void *)((uintptr_t)pci_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0) & ~0xf);
+	reg_base = (void *)((uintptr_t)pci_read_config32(SA_DEV_IGD,
+		PCI_BASE_ADDRESS_0) & ~0xf);
 
 	/* Check if backlight is enabled */
 	pp_ctrl = read32(reg_base + PCH_PP_CONTROL);

src/soc/intel/broadwell/smmrelocate.c

@@ -224,7 +224,8 @@ static void fill_in_relocation_params(device_t dev,
 	/* SMRR has 32-bits of valid address aligned to 4KiB. */
 	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
 	params->smrr_base.hi = 0;
-	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
+		| MTRR_PHYS_MASK_VALID;
 	params->smrr_mask.hi = 0;
 
 	/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
@@ -235,7 +236,8 @@ static void fill_in_relocation_params(device_t dev,
 	 * on the number of physical address bits supported. */
 	params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
 	params->emrr_base.hi = 0;
-	params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
+	params->emrr_mask.lo = (~(emrr_size - 1) & rmask)
+		| MTRR_PHYS_MASK_VALID;
 	params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
 
 	/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */

src/soc/intel/broadwell/spi.c

@@ -421,7 +421,8 @@ static int spi_setup_offset(spi_transaction *trans)
 		spi_use_out(trans, 3);
 		return 1;
 	default:
-		printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
+		printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n",
+			trans->type);
 		return -1;
 	}
 }
@@ -533,7 +534,8 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 			return -1;
 
 		if (status & SPIS_FCERR) {
-			printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
+			printk(BIOS_DEBUG,
+				"ICH SPI: Command transaction error\n");
 			return -1;
 		}
 
@@ -548,8 +550,8 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 	 * by the SPI chip driver.
 	 */
 	if (trans.bytesout > cntlr.databytes) {
-		printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
+		printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI"
-		     " CONTROLLER_PAGE_LIMIT?\n");
+		     " chip driver use CONTROLLER_PAGE_LIMIT?\n");
 		return -1;
 	}
 
@@ -561,7 +563,10 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 		uint32_t data_length;
 
 		/* SPI addresses are 24 bit only */
-		/* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf */
+		/* http://www.intel.com/content/dam/www/public/us/en/documents/
+		 * datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-
+		 * n2806-j1850-j1750-datasheet.pdf
+		 */
 		writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
 
 		if (trans.bytesout)