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soc/intel/broadwell: Fix {}, () and conditional issues 

Fix the following errors and warnings detected by checkpatch:

ERROR: open brace '{' following struct go on the same line
ERROR: return is not a function, parentheses are not required
ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement

TEST=None

Change-Id: I9414341b0c778c252db33f0ef4847b9530681d96
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18884
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Lee Leahy 2017-03-17 10:43:25 -07:00
parent 23602dfd68
commit 8a9c7dc087
12 changed files with 74 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/broadwell/cpu.c
View File

@ -688,9 +688,8 @@ void broadwell_init_cpus(device_t dev)
{
struct bus *cpu_bus = dev->link_list;
if (mp_init_with_smm(cpu_bus, &mp_ops)) {
if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
}
}
static struct device_operations cpu_dev_ops = {

5
src/soc/intel/broadwell/igd.c
View File

@ -530,11 +530,10 @@ static void igd_init(struct device *dev)
/* Late init steps */
igd_cdclk_init(dev, is_broadwell);
if (is_broadwell) {
if (is_broadwell)
reg_script_run_on_dev(dev, broadwell_late_init_script);
} else {
else
reg_script_run_on_dev(dev, haswell_late_init_script);
}
if (gfx_get_init_done()) {
/*

3
src/soc/intel/broadwell/include/soc/pei_data.h
View File

@ -86,8 +86,7 @@ struct usb3_port_setting {
uint8_t fixed_eq;
} __attribute__((packed));
struct pei_data
{
struct pei_data {
uint32_t pei_version;
enum board_type board_type;

16
src/soc/intel/broadwell/lpc.c
View File

@ -114,10 +114,18 @@ static void pch_pirq_init(device_t dev)
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
case 1: /* INTA# */ int_line = config->pirqa_routing; break;
case 2: /* INTB# */ int_line = config->pirqb_routing; break;
case 3: /* INTC# */ int_line = config->pirqc_routing; break;
case 4: /* INTD# */ int_line = config->pirqd_routing; break;
case 1: /* INTA# */
int_line = config->pirqa_routing;
break;
case 2: /* INTB# */
int_line = config->pirqb_routing;
break;
case 3: /* INTC# */
int_line = config->pirqc_routing;
break;
case 4: /* INTD# */
int_line = config->pirqd_routing;
break;
}
if (!int_line)

7
src/soc/intel/broadwell/me.c
View File

@ -647,10 +647,8 @@ static int me_icc_set_clock_enables(u32 mask)
if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
return -1;
} else {
printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
}
printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
return 0;
}
@ -916,9 +914,8 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
#if CONFIG_DEBUG_INTEL_ME
printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
mbp->header.num_entries, mbp->header.mbp_size);
for (i = 0; i < mbp->header.mbp_size - 1; i++) {
for (i = 0; i < mbp->header.mbp_size - 1; i++)
printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]);
}
#endif
#define ASSIGN_FIELD_PTR(field_, val_) \

3
src/soc/intel/broadwell/refcode.c
View File

@ -48,9 +48,8 @@ static pei_wrapper_entry_t load_reference_code(void)
.prog = &prog,
};
if (acpi_is_wakeup_s3()) {
if (acpi_is_wakeup_s3())
return load_refcode_from_cache();
}
if (prog_locate(&prog)) {
printk(BIOS_DEBUG, "Couldn't locate reference code.\n");

5
src/soc/intel/broadwell/romstage/romstage.c
View File

@ -123,14 +123,15 @@ void asmlinkage romstage_after_car(void)
{
/* Load the ramstage. */
run_ramstage();
while (1);
while (1)
;
}
int get_sw_write_protect_state(void)
{
u8 status;
/* Return unprotected status if status read fails. */
return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
return early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80);
}
void __attribute__((weak)) mainboard_pre_console_init(void) {}

10
src/soc/intel/broadwell/smbus_common.c
View File

@ -62,9 +62,9 @@ int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
unsigned char global_status_register;
unsigned char byte;
if (smbus_wait_until_ready(smbus_base) < 0) {
if (smbus_wait_until_ready(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
/* Setup transaction */
/* Disable interrupts */
outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
@ -86,9 +86,8 @@ int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
smbus_base + SMBHSTCTL);
/* Poll for transaction completion */
if (smbus_wait_until_done(smbus_base) < 0) {
if (smbus_wait_until_done(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
global_status_register = inb(smbus_base + SMBHSTSTAT);
@ -97,9 +96,8 @@ int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
/* Read results of transaction */
byte = inb(smbus_base + SMBHSTDAT0);
if (global_status_register != (1 << 1)) {
if (global_status_register != (1 << 1))
return SMBUS_ERROR;
}
return byte;
}

9
src/soc/intel/broadwell/smihandler.c
View File

@ -427,7 +427,8 @@ static void southbridge_smi_tco(void)
if (!tco_sts)
return;
if (tco_sts & (1 << 8)) { // BIOSWR
// BIOSWR
if (tco_sts & (1 << 8)) {
u8 bios_cntl = pci_read_config16(PCH_DEV_LPC, BIOS_CNTL);
if (bios_cntl & 1) {
@ -491,7 +492,8 @@ static void southbridge_smi_monitor(void)
/* IOTRAP(0) SMIC */
if (IOTRAP(0)) {
if (!(trap_cycle & (1 << 24))) { // It's a write
// It's a write
if (!(trap_cycle & (1 << 24))) {
printk(BIOS_DEBUG, "SMI1 command\n");
data = RCBA32(0x1e18);
data &= mask;
@ -505,7 +507,8 @@ static void southbridge_smi_monitor(void)
printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
trap_cycle & 0xfffc);
for (i = 0; i < 4; i++)
if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
if (IOTRAP(i))
printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n",

3
src/soc/intel/broadwell/smmrelocate.c
View File

@ -292,9 +292,8 @@ void smm_initialize(void)
*/
smm_initiate_relocation();
if (smm_reloc_params.smm_save_state_in_msrs) {
if (smm_reloc_params.smm_save_state_in_msrs)
printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
}
}
/* The default SMM entry can happen in parallel or serially. If the

78
src/soc/intel/broadwell/spi.c
View File

@ -367,43 +367,43 @@ static int spi_setup_opcode(spi_transaction *trans)
optypes = (optypes & 0xfffc) | (trans->type & 0x3);
writew_(optypes, cntlr.optype);
return 0;
} else {
/* The lock is on. See if what we need is on the menu. */
uint8_t optype;
uint16_t opcode_index;
/* Write Enable is handled as atomic prefix */
if (trans->opcode == SPI_OPCODE_WREN)
return 0;
read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
for (opcode_index = 0; opcode_index < cntlr.menubytes;
opcode_index++) {
if (opmenu[opcode_index] == trans->opcode)
break;
}
if (opcode_index == cntlr.menubytes) {
printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
trans->opcode);
return -1;
}
optypes = readw_(cntlr.optype);
optype = (optypes >> (opcode_index * 2)) & 0x3;
if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
trans->bytesout >= 3) {
/* We guessed wrong earlier. Fix it up. */
trans->type = optype;
}
if (optype != trans->type) {
printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
optype);
return -1;
}
return opcode_index;
}
/* The lock is on. See if what we need is on the menu. */
uint8_t optype;
uint16_t opcode_index;
/* Write Enable is handled as atomic prefix */
if (trans->opcode == SPI_OPCODE_WREN)
return 0;
read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
for (opcode_index = 0; opcode_index < cntlr.menubytes;
opcode_index++) {
if (opmenu[opcode_index] == trans->opcode)
break;
}
if (opcode_index == cntlr.menubytes) {
printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
trans->opcode);
return -1;
}
optypes = readw_(cntlr.optype);
optype = (optypes >> (opcode_index * 2)) & 0x3;
if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
trans->bytesout >= 3) {
/* We guessed wrong earlier. Fix it up. */
trans->type = optype;
}
if (optype != trans->type) {
printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
optype);
return -1;
}
return opcode_index;
}
static int spi_setup_offset(spi_transaction *trans)
@ -489,9 +489,11 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
spi_setup_type(&trans);
if ((opcode_index = spi_setup_opcode(&trans)) < 0)
opcode_index = spi_setup_opcode(&trans);
if (opcode_index < 0)
return -1;
if ((with_address = spi_setup_offset(&trans)) < 0)
with_address = spi_setup_offset(&trans);
if (with_address < 0)
return -1;
if (trans.opcode == SPI_OPCODE_WREN) {

3
src/soc/intel/broadwell/systemagent.c
View File

@ -256,9 +256,8 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
static void mc_read_map_entries(device_t dev, uint64_t *values)
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
for (i = 0; i < NUM_MAP_ENTRIES; i++)
read_map_entry(dev, &memory_map[i], &values[i]);
}
}
static void mc_report_map_entries(device_t dev, uint64_t *values)