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google/kahlee: Update for single DIMM 

Update for a single DIMM with an SPD at address A0.

Change-Id: I646f079c99cbaffd7094773243600c3030308325
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19833
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2017-06-23 13:07:10 -06:00 committed by Martin Roth
parent a9d3d65a92
commit 6f174ee0dd
2 changed files with 3 additions and 3 deletions
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2
src/mainboard/google/kahlee/OemCustomize.c
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@ -20,7 +20,7 @@
static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
MOTHER_BOARD_LAYERS(LAYERS_6), MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,

4
src/mainboard/google/kahlee/devicetree.cb
View File

@ -16,7 +16,7 @@ chip soc/amd/stoneyridge
register "spdAddrLookup" = " register "spdAddrLookup" = "
{ {
{ {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1 { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
}" }"
device cpu_cluster 0 on device cpu_cluster 0 on
@ -41,7 +41,7 @@ chip soc/amd/stoneyridge
device pci 12.0 on end # EHCI device pci 12.0 on end # EHCI
device pci 14.0 on # SM device pci 14.0 on # SM
chip drivers/generic/generic # dimm 0-0-0 chip drivers/generic/generic # dimm 0-0-0
device i2c 51 on end device i2c 50 on end
end end
end # SM end # SM
device pci 14.3 on end # LPC 0x790e device pci 14.3 on end # LPC 0x790e