mb/ocp/deltalake: replace "POST complete" mb code with driver functionality
Replace the mainboard-specific code for "POST complete" signalling with devicetree entries for using the newly introduced IPMI driver functionality. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Tested successfully. Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Change-Id: I3441c2a971cfb564b34b3a419beceb949fe295b1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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2 changed files with 4 additions and 10 deletions
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@ -51,6 +51,7 @@ chip soc/intel/xeon_sp/cpx
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end
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device domain 0 on
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device gpio 0 alias pch_gpio on end
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device pci 00.0 on end # Host bridge
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device pci 04.0 on end # Intel SkyLake-E CBDMA Registers
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device pci 04.1 on end # Intel SkyLake-E CBDMA Registers
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@ -86,8 +87,11 @@ chip soc/intel/xeon_sp/cpx
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device pci 1f.0 on
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chip drivers/ipmi # BMC KCS
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device pnp ca2.0 on end
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use pch_gpio as gpio_dev
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register "bmc_i2c_address" = "0x20"
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register "bmc_boot_timeout" = "60"
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register "post_complete_gpio" = "GPP_B20"
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register "post_complete_invert" = "1"
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end
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chip drivers/ipmi/ocp # OCP specific IPMI porting
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device pnp ca2.1 on end
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@ -5,8 +5,6 @@
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#include <bootstate.h>
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#include <drivers/ipmi/ipmi_ops.h>
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#include <drivers/ocp/dmi/ocp_dmi.h>
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#include <gpio.h>
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#include <soc/lewisburg_pch_gpio_defs.h>
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#include <soc/ramstage.h>
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#include <soc/soc_util.h>
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#include <stdio.h>
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@ -367,11 +365,3 @@ struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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.final = mainboard_final,
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};
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static void pull_post_complete_pin(void *unused)
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{
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/* Pull Low post complete pin */
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gpio_output(GPP_B20, 0);
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}
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL);
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