usbdebug: Remove EHCI_DEBUG_OFFSET
Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -569,6 +569,8 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_
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int port_map_tried;
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int playtimes = 3;
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dprintk(BIOS_INFO, "ehci_bar: 0x%x debug_offset 0x%x\n", ehci_bar, offset);
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ehci_caps = (struct ehci_caps *)ehci_bar;
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ehci_regs = (struct ehci_regs *)(ehci_bar +
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HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
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@ -589,7 +591,6 @@ try_next_port:
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debug_port = HCS_DEBUG_PORT(hcs_params);
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n_ports = HCS_N_PORTS(hcs_params);
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dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar);
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dprintk(BIOS_INFO, "debug_port: %d\n", debug_port);
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dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
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@ -926,11 +927,13 @@ struct dbgp_pipe *dbgp_console_input(void)
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int usbdebug_init(void)
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{
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struct ehci_debug_info *dbg_info = dbgp_ehci_info();
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unsigned int ehci_base, dbg_offset;
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#if !defined(__PRE_RAM__) && !defined(__SMM__)
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if (!get_usbdebug_from_cbmem(dbg_info))
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return 0;
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#endif
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ehci_debug_hw_enable();
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return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
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if (ehci_debug_hw_enable(&ehci_base, &dbg_offset))
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return -1;
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return usbdebug_init_(ehci_base, dbg_offset, dbg_info);
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}
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@ -24,10 +24,12 @@
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void usbdebug_re_enable(unsigned ehci_base);
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void usbdebug_disable(void);
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void ehci_debug_hw_enable(void);
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/* Returns 0 on success and sets MMIO base and dbg_offset if EHCI debug
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* capability was found and enabled. Returns non-zero on error.
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*/
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int ehci_debug_hw_enable(unsigned *base, unsigned *dbg_offset);
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void ehci_debug_select_port(unsigned int port);
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#define DBGP_EP_VALID (1<<0)
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#define DBGP_EP_ENABLED (1<<1)
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#define DBGP_EP_BUSY (1<<2)
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@ -34,12 +34,30 @@ static struct device_operations *ehci_drv_ops;
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static struct device_operations ehci_dbg_ops;
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#endif
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void ehci_debug_hw_enable(void)
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int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
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{
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#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE
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pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
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pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev = dbg_dev;
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#else
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device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev));
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#endif
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u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
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if (!pos)
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return -1;
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u32 cap = pci_read_config32(dev, pos);
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/* FIXME: We should remove static EHCI_BAR_INDEX. */
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u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1);
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if (dbg_bar != EHCI_BAR_INDEX)
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return -1;
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*base = CONFIG_EHCI_BAR;
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*dbg_offset = (cap>>16) & 0x1ffc;
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return 0;
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}
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void ehci_debug_select_port(unsigned int port)
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@ -43,10 +43,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xe0
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config HUDSON_XHCI_ENABLE
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bool "Enable Hudson XHCI Controller"
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default y
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@ -54,10 +54,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xe0
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/amd/cimx/sb700/bootblock.c"
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@ -209,10 +209,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xe0
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choice
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prompt "Fan Control"
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default SB800_NO_FAN_CONTROL
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@ -32,10 +32,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xe0
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choice
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prompt "SATA Mode"
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default SATA_MODE_IDE
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@ -45,8 +45,4 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xe0
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endif # SOUTHBRIDGE_AMD_SB700
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@ -37,8 +37,4 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xe0
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endif # SOUTHBRIDGE_AMD_SB800
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@ -41,10 +41,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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config DRAM_RESET_GATE_GPIO
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int
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default 60
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@ -37,10 +37,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/fsp_bd82x6x/bootblock.c"
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@ -33,8 +33,4 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0x80
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endif
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@ -11,8 +11,4 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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endif
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@ -32,10 +32,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/i82801gx/bootblock.c"
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@ -33,10 +33,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/i82801ix/bootblock.c"
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@ -39,10 +39,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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config DRAM_RESET_GATE_GPIO
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int
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default 60
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@ -44,10 +44,6 @@ config EHCI_BAR
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hex
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default 0xe8000000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/lynxpoint/bootblock.c"
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@ -30,10 +30,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0xa0
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config HAVE_CMC
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bool "Add a CMC state machine binary"
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help
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@ -14,10 +14,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0x98
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config CK804_USE_NIC
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bool
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default n
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@ -14,10 +14,6 @@ config EHCI_BAR
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hex
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default 0xfef00000
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config EHCI_DEBUG_OFFSET
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hex
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default 0x98
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config MCP55_USE_NIC
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bool
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default n
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@ -12,6 +12,3 @@ config EHCI_BAR
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hex
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default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
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config EHCI_DEBUG_OFFSET
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hex
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default 0x98 if SOUTHBRIDGE_SIS_SIS966
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