GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0 

DMIC's are now connected to DMIC_CLK0/DMIC_DATA0.
So, enable the pins accordingly.

BUG=b:113744731,b:111106010
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image

Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/28433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Sathyanarayana Nujella 2018-09-02 09:11:28 -07:00 committed by Patrick Georgi
parent 55597ff279
commit 6f70d51fac
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/poppy/variants/nocturne/gpio.c
View File

@ -199,10 +199,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* D18 : DMIC_DATA1 ==> PCH_DMIC_DATA */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* D19 : DMIC_CLK0 ==> NC */
PAD_CFG_NC(GPP_D19),
/* D20 : DMIC_DATA0 ==> NC */
PAD_CFG_NC(GPP_D20),
/* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
/* D21 : SPI1_IO2 ==> NC */
PAD_CFG_NC(GPP_D21),
/* D22 : SPI1_IO3 ==> NC */