mb/intel/adlrvp: Add initial code for adlrvp with raptorlake silicon

Take adlrvp_p as a baseline code and add a new variant of ADL RVP
with Raptor Lake silicon.

BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I880abe0f300118f461523173cc0d50a2fbc99e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

src/mainboard/intel/adlrvp/Kconfig

@@ -32,6 +32,13 @@ config BOARD_INTEL_ADLRVP_P_EXT_EC
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select GEN3_EXTERNAL_CLOCK_BUFFER
 
+config BOARD_INTEL_ADLRVP_RPL_EXT_EC
+	select BOARD_INTEL_ADLRVP_COMMON
+	select DRIVERS_INTEL_PMC
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select GEN3_EXTERNAL_CLOCK_BUFFER
+
 config BOARD_INTEL_ADLRVP_P_MCHP
 	select BOARD_INTEL_ADLRVP_COMMON
 	select DRIVERS_INTEL_MIPI_CAMERA
@@ -88,6 +95,7 @@ config MAINBOARD_DIR
 config VARIANT_DIR
 	default "adlrvp_p" if BOARD_INTEL_ADLRVP_P
 	default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC
+	default "adlrvp_rpl_ext_ec" if BOARD_INTEL_ADLRVP_RPL_EXT_EC
 	default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP
 	default "adlrvp_m" if BOARD_INTEL_ADLRVP_M
 	default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC
@@ -126,7 +134,7 @@ config DIMM_SPD_SIZE
 choice
 	prompt "ON BOARD EC"
 	default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_N
-	default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC
+	default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC
 	help
 	  This option allows you to select the on board EC to use.
 	  Select whether the board has Intel EC or Chrome EC
@@ -146,7 +154,7 @@ endchoice
 
 config VBOOT
 	select VBOOT_LID_SWITCH
-	select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC
+	select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_P_EXT_EC
 	select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC
 	select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC
 

src/mainboard/intel/adlrvp/Kconfig.name

@@ -18,3 +18,6 @@ config BOARD_INTEL_ADLRVP_N
 
 config BOARD_INTEL_ADLRVP_N_EXT_EC
 	bool "Alderlake-N RVP with Chrome EC"
+
+config BOARD_INTEL_ADLRVP_RPL_EXT_EC
+	bool "Raptorlake silicon with Alderlake-P RVP and Chrome EC"

src/mainboard/intel/adlrvp/chromeos.c

@@ -15,7 +15,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
 	};
 	if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) ||
-		CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC))
+		CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
 		lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 	else
 		lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1);
@@ -41,7 +41,7 @@ int get_write_protect_state(void)
 }
 
 #if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) ||\
-	CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC))
+	CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
 int get_ec_is_trusted(void)
 {
 	/* EC is trusted if not in RW. */

src/mainboard/intel/adlrvp/ramstage.c

@@ -80,7 +80,8 @@ static const struct board_id_iom_port_config {
 static void variant_update_typec_init_config(void)
 {
 	/* Skip filling aux bias gpio pads for Windows SKUs */
-	if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC)))
+	if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC)
+		|| CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)))
 		return;
 
 	config_t *config = config_of_soc();

src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb

@@ -0,0 +1,61 @@
+chip soc/intel/alderlake
+
+	device domain 0 on
+		device ref pch_espi on
+			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				use conn2 as mux_conn[2]
+				device pnp 0c09.0 on end
+			end
+		end
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TypeC Port 1""
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""TypeC Port 2""
+						device ref tcss_usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""TypeC Port 3""
+						device ref tcss_usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref pmc hidden
+			# The pmc_mux chip driver is a placeholder for the
+			# PMC.MUX device in the ACPI hierarchy.
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 1 alias conn1 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port3 as usb3_port
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 2 alias conn2 on end
+					end
+				end
+			end
+		end
+	end
+end