soc/apollolake: Correct the comment section in gpio.asl
This patch corrects the comment section in gpio.asl for GPE method. Change-Id: I45771a295ee1eda00b9699f42cddd120223ff7bf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16647 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -191,7 +191,8 @@ scope (\_SB) {
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Scope(\_GPE)
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{
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/* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
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/*
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* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
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* _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable
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* register at 0x430. For APL ACPI enable register DW0 i.e., ACPI
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* GPE0a_EN at 0x430 is reserved.
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