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soc/mediatek/mt8186: Use BIT() macro for arbiter enable bit 

Replace (1 << x) with BIT(x) in pmic_wrap.h.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I463589f02065a228a8af74447b4586e5b54e0b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61351
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Rex-BC Chen 2022-01-25 09:53:12 +08:00 committed by Hung-Te Lin
parent af2f8b9297
commit 707aa2ae77
1 changed files with 20 additions and 20 deletions
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40
src/soc/mediatek/mt8186/include/soc/pmic_wrap.h
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@ -362,26 +362,26 @@ enum {
};
enum {
ARB_WACS0 = 0x1 << 0,
ARB_WACS1 = 0x1 << 1,
ARB_WACS2 = 0x1 << 2,
ARB_WACS3 = 0x1 << 3,
ARB_WACS_P2P = 0x1 << 4,
ARB_WACS_MD32 = 0x1 << 5,
ARB_MDINF = 0x1 << 6,
ARB_C2KINF = 0x1 << 7,
ARB_MD_DVFSINF = 0x1 << 8,
ARB_SPMINF = 0x1 << 9,
ARB_SPMINF_BACKUP = 0x1 << 10,
ARB_SRCLKEN_RCINF = 0x1 << 11,
ARB_DCXO_CONNINF = 0x1 << 12,
ARB_DCXO_NFCINF = 0x1 << 13,
ARB_MCU_PMINF = 0x1 << 14,
ARB_MD_ADCINF_0 = 0x1 << 15,
ARB_MD_ADCINF_1 = 0x1 << 16,
ARB_GPSINF_0 = 0x1 << 17,
ARB_GPSINF_1 = 0x1 << 18,
ARB_STAUPD = 0x1 << 19,
ARB_WACS0 = BIT(0),
ARB_WACS1 = BIT(1),
ARB_WACS2 = BIT(2),
ARB_WACS3 = BIT(3),
ARB_WACS_P2P = BIT(4),
ARB_WACS_MD32 = BIT(5),
ARB_MDINF = BIT(6),
ARB_C2KINF = BIT(7),
ARB_MD_DVFSINF = BIT(8),
ARB_SPMINF = BIT(9),
ARB_SPMINF_BACKUP = BIT(10),
ARB_SRCLKEN_RCINF = BIT(11),
ARB_DCXO_CONNINF = BIT(12),
ARB_DCXO_NFCINF = BIT(13),
ARB_MCU_PMINF = BIT(14),
ARB_MD_ADCINF_0 = BIT(15),
ARB_MD_ADCINF_1 = BIT(16),
ARB_GPSINF_0 = BIT(17),
ARB_GPSINF_1 = BIT(18),
ARB_STAUPD = BIT(19),
ARB_USER_EN = ARB_WACS0 | ARB_WACS1 | ARB_WACS2 | ARB_WACS3 |
ARB_WACS_P2P | ARB_WACS_MD32 | ARB_MDINF |
ARB_MD_DVFSINF | ARB_SPMINF |