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soc/intel/alderlake: Choose non-posted write to lock GPIO PAD 

Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI config on Alder Lake
to instruct Pad Configuration Lock to use non-posted sideband writes as
posted write is not supported on Alder Lake while locking GPIO pads.

BUG=b:211573253, b:211950520
TEST=None

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id8d394b97de9c328b3f75df3649d7efc782f006b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-01-10 10:26:52 +00:00
parent 393b093f71
commit af2f8b9297
1 changed files with 1 additions and 0 deletions
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1
src/soc/intel/alderlake/Kconfig
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@ -73,6 +73,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
select SOC_INTEL_COMMON_BLOCK_DTT
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_IPU