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mb/up/squared: do UART pad configuration at board-level 

UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I357099f797be178543a9e6637335cd0a68633071
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49441
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-12-21 03:46:58 +01:00
parent 18d360a582
commit 70992a4335
3 changed files with 35 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/up/squared/bootblock.c
View File

@ -1,11 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <intelblocks/gpio.h>
#include <soc/gpio.h>
#include "gpio_early.h"
void bootblock_mainboard_init(void)
void bootblock_mainboard_early_init(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

19
src/mainboard/up/squared/gpio.h
View File

@ -756,6 +756,25 @@ static const struct pad_config gpio_table[] = {
/* LPC_FRAMEB - LPC_FRAMEB */
PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
/* ------- GPIO Group North ------- */
/*
* LPSS UART
* Note: It's unconfirmed if this redundancy to the bootblock table is necessary.
*/
/* GPIO_38 - LPSS_UART0_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
/* GPIO_39 - LPSS_UART0_TXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
/* GPIO_42 - LPSS_UART1_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
/* GPIO_43 - LPSS_UART1_TXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD),
};
#endif /* CFG_GPIO_H */

14
src/mainboard/up/squared/gpio_early.h
View File

@ -34,6 +34,20 @@ static const struct pad_config early_gpio_table[] = {
/* LPC_FRAMEB - LPC_FRAMEB */
PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
/* ------- GPIO Group North ------- */
/* GPIO_38 - LPSS_UART0_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
/* GPIO_39 - LPSS_UART0_TXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
/* GPIO_42 - LPSS_UART1_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
/* GPIO_43 - LPSS_UART1_TXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD),
};
#endif /* CFG_GPIO_EARLY_H */