soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly

The original code only reserves IOM mmio, but there is other asl
code that requires to program ioe p2sb mmio such as IOE PCIE clk request
control. See \_SB.ECLK.CLKD in src/soc/intel/common/acpi/pcie_clk.asl

TEST=as before: suspend_stress_test 50 cycle pass, type-c display OK
on screebo

Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78252
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Kane Chen 2023-10-05 14:03:53 +08:00 committed by Felix Held
parent 0177c95c16
commit 70b517ee57
1 changed files with 2 additions and 2 deletions

View File

@ -34,8 +34,8 @@ void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
static void ioe_p2sb_read_resources(struct device *dev)
{
/* Add the fixed MMIO resource for IOM */
mmio_range(dev, PCI_BASE_ADDRESS_0, IOM_BASE_ADDR, IOM_BASE_SIZE);
/* Add the fixed MMIO resource for IOE P2SB */
mmio_range(dev, PCI_BASE_ADDRESS_0, IOE_P2SB_BAR, IOE_P2SB_SIZE);
}
static void p2sb_read_resources(struct device *dev)