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soc/intel/jasperlake: Drop unreferenced devicetree settings 

No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: I40eba4128f1c5bafc7023b28dbaf40c0aca3f490
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Angel Pons 2020-12-11 16:48:47 +01:00 committed by Hung-Te Lin
parent 030db31aa8
commit 70d8baef92
1 changed files with 0 additions and 9 deletions
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9
src/soc/intel/jasperlake/chip.h
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@ -129,22 +129,13 @@ struct soc_intel_jasperlake_config {
/* Enable if SD Card Power Enable Signal is Active High */ /* Enable if SD Card Power Enable Signal is Active High */
uint8_t SdCardPowerEnableActiveHigh; uint8_t SdCardPowerEnableActiveHigh;
/* Integrated Sensor */
uint8_t PchIshEnable;
/* Heci related */
uint8_t Heci3Enabled;
/* VR Config Settings for IA Core */ /* VR Config Settings for IA Core */
uint16_t ImonSlope; uint16_t ImonSlope;
uint16_t ImonOffset; uint16_t ImonOffset;
/* Gfx related */ /* Gfx related */
uint8_t IgdDvmt50PreAlloc;
uint8_t SkipExtGfxScan; uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr;
/* HeciEnabled decides the state of Heci1 at end of boot /* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */ * Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled; uint8_t HeciEnabled;