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nb/intel/sandybridge: Use MCHBAR bitwise ops 

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: If16d8c4aef3dfd1dbeaf48d6855dd4c0ef328168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons 2020-06-07 19:30:26 +02:00 committed by Felix Held
parent 9733f6a336
commit 71892b4bec
1 changed files with 5 additions and 15 deletions
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20
src/northbridge/intel/sandybridge/early_init.c
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@ -62,7 +62,6 @@ static void sandybridge_setup_bars(void)
static void sandybridge_setup_graphics(void) static void sandybridge_setup_graphics(void)
{ {
u32 reg32;
u16 reg16; u16 reg16;
u8 gfxsize; u8 gfxsize;
@ -106,27 +105,18 @@ static void sandybridge_setup_graphics(void)
pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
/* Erratum workarounds */ /* Erratum workarounds */
reg32 = MCHBAR32(SAPMCTL); MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10));
reg32 |= (1 << 9) | (1 << 10);
MCHBAR32(SAPMCTL) = reg32;
/* Enable SA Clock Gating */ /* Enable SA Clock Gating */
reg32 = MCHBAR32(SAPMCTL); MCHBAR32_OR(SAPMCTL, 1);
MCHBAR32(SAPMCTL) = reg32 | 1;
/* GPU RC6 workaround for sighting 366252 */ /* GPU RC6 workaround for sighting 366252 */
reg32 = MCHBAR32(SSKPD_HI); MCHBAR32_OR(SSKPD_HI, 1 << 31);
reg32 |= (1 << 31);
MCHBAR32(SSKPD_HI) = reg32;
/* VLW (Virtual Legacy Wire?) */ /* VLW (Virtual Legacy Wire?) */
reg32 = MCHBAR32(0x6120); MCHBAR32_AND(0x6120, ~(1 << 0));
reg32 &= ~(1 << 0);
MCHBAR32(0x6120) = reg32;
reg32 = MCHBAR32(INTRDIRCTL); MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5));
reg32 |= (1 << 4) | (1 << 5);
MCHBAR32(INTRDIRCTL) = reg32;
} }
static void start_peg_link_training(void) static void start_peg_link_training(void)