GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

include/cpu/amd/msr: add and use MC_CTL_MASK macro 

Add this macro to be able to conveniently access the MC_CTL_MASK
register for each MCA bank. Also drop the unused definitions for
MC1_CTL_MASK and MC4_CTL_MASK.

Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-07-13 18:31:40 +02:00
parent 4f51c94099
commit 71b918d882
2 changed files with 3 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/include/cpu/amd/msr.h
View File

@ -19,8 +19,7 @@
#define NB_CFG_MSR 0xC001001f
#define FidVidStatus 0xC0010042
#define MC0_CTL_MASK 0xC0010044
#define MC1_CTL_MASK 0xC0010045
#define MC4_CTL_MASK 0xC0010048
#define MC_CTL_MASK(bank) (MC0_CTL_MASK + (bank))
#define MSR_INTPEND 0xC0010055
#define MMIO_CONF_BASE 0xC0010058
#define MMIO_RANGE_EN (1 << 0)

5
src/soc/amd/stoneyridge/mca.c
View File

@ -123,8 +123,7 @@ static void build_bert_mca_error(struct mca_bank_status *mci)
ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4);
if (!ctx)
goto failed;
ctx = cper_new_ia32x64_context_msr(status, x86_sec,
MC0_CTL_MASK + mci->bank, 1);
ctx = cper_new_ia32x64_context_msr(status, x86_sec, MC_CTL_MASK(mci->bank), 1);
if (!ctx)
goto failed;
@ -160,7 +159,7 @@ static void mca_print_error(unsigned int bank)
printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(IA32_MC_CTL(bank));
printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(MC0_CTL_MASK + bank);
msr = rdmsr(MC_CTL_MASK(bank));
printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo);
}