added pll_reset.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Li-Ta Lo
parent
a413ecc6cd
commit
71e3326b9c
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#include <cpu/x86/tsc.h>
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#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
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#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
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#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */
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static unsigned int calibrate_tsc(void)
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{
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/* Set the Gate high, disable speaker */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/*
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* Now let's take care of CTC channel 2
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*
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* Set the Gate high, program CTC channel 2 for mode 0,
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* (interrupt on terminal count mode), binary count,
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* load 5 * LATCH count, (LSB and MSB) to begin countdown.
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*/
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outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
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outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */
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outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */
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{
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tsc_t start;
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tsc_t end;
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unsigned long count;
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start = rdtsc();
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count = 0;
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do {
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count++;
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} while ((inb(0x61) & 0x20) == 0);
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end = rdtsc();
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/* Error: ECTCNEVERSET */
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if (count <= 1)
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goto bad_ctc;
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/* 64-bit subtract - gcc just messes up with long longs */
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__asm__("subl %2,%0\n\t"
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"sbbl %3,%1"
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:"=a" (end.lo), "=d" (end.hi)
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:"g" (start.lo), "g" (start.hi),
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"0" (end.lo), "1" (end.hi));
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/* Error: ECPUTOOFAST */
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if (end.hi)
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goto bad_ctc;
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/* Error: ECPUTOOSLOW */
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if (end.lo <= CALIBRATE_DIVISOR)
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goto bad_ctc;
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return (end.lo + CALIBRATE_DIVISOR -1)/CALIBRATE_DIVISOR;
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}
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/*
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* The CTC wasn't reliable: we got a hit on the very first read,
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* or the CPU was so fast/slow that the quotient wouldn't fit in
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* 32 bits..
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*/
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bad_ctc:
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print_err("bad_ctc\n");
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return 0;
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}
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/* spll_raw_clk = SYSREF * FbDIV,
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* GLIU Clock = spll_raw_clk / MDIV
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* CPU Clock = sppl_raw_clk / VDIV
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*/
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/* table for Feedback divisor to FbDiv register value */
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static const unsigned char plldiv2fbdiv[] = {
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0, 0, 0, 0, 0, 0, 15, 7, 3, 1, 0, 32, 16, 40, 20, 42, /* pll div 0 - 15 */
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21, 10, 37, 50, 25, 12, 38, 19, 9, 4, 34, 17, 8, 36, 18, 41, /* pll div 16 - 31 */
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52, 26, 45, 54, 27, 13, 6, 35, 49, 56, 28, 46, 23, 11, 05, 02, /* pll div 32 - 47 */
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33, 48, 24, 44, 22, 43, 53, 58, 29, 14, 39, 51, 57, 60, 30, 47, /* pll div 48 - 63 */
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};
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/* table for FbDiv register value to Feedback divisor */
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static const unsigned char fbdiv2plldiv[] = {
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10, 9, 47, 8, 25, 46, 38, 7, 28, 24, 17, 45, 21, 37, 57, 6,
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12, 27, 30, 23, 14, 16, 52, 44, 50, 20, 33, 36, 42, 56, 0, 0,
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11, 48, 26, 39, 29, 18, 22, 58, 13, 31, 15, 53, 51, 34, 43, 0,
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49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0
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};
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#if 1
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static void get_memory_speed(void)
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{
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unsigned char val;
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val = do_smbus_read_byte(0x6000, 0xA0, 0);
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print_debug("SPD byte ");
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print_debug_hex8(0);
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print_debug(" = ");
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print_debug_hex8(val);
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print_debug("\r\n");
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val = do_smbus_read_byte(0x6000, 0xA0, 1);
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print_debug("SPD byte ");
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print_debug_hex8(1);
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print_debug(" = ");
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print_debug_hex8(val);
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print_debug("\r\n");
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val = do_smbus_read_byte(0x6000, 0xA0, 2);
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print_debug("SPD byte ");
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print_debug_hex8(2);
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print_debug(" = ");
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print_debug_hex8(val);
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print_debug("\r\n");
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}
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#endif
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static void pll_reset(void)
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{
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msr_t msr;
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unsigned int sysref, spll_raw, cpu_core, gliu;
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unsigned mdiv, vdiv, fbdiv;
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/* get CPU core clock in MHZ */
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cpu_core = calibrate_tsc();
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get_memory_speed();
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//msr = rdmsr(GLCP_SYS_RSTPLL);
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msr = rdmsr(0x4c000014);
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if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
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print_debug("disable PLL bypass\n\r");
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msr.hi = 0x00001490;
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msr.lo = 0x02000030;
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wrmsr(GLCP_SYS_RSTPLL, msr);
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msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
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wrmsr(GLCP_SYS_RSTPLL, msr);
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print_debug("Reset PLL\n\r");
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msr.lo |= ((1<<14) |(1<<13) | (1<<0));
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wrmsr(GLCP_SYS_RSTPLL,msr);
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print_debug("should not be here\n\r");
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}
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if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) {
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/* PLL is already set and we are reboot from PLL reset */
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print_debug("reboot from BIOS reset\n\r");
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return;
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}
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print_debug("prgramming PLL\n\r");
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vdiv = (msr.hi >> GLCP_SYS_RSTPLL_VDIV_SHIFT) & 0x07;
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vdiv += 2;
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fbdiv = (msr.hi >> GLCP_SYS_RSTPLL_FBDIV_SHIFT) & 0x3f;
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fbdiv = fbdiv2plldiv[fbdiv];
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spll_raw = cpu_core * vdiv;
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sysref = spll_raw / fbdiv;
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print_debug("SYSREF/PCI Clock ");
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print_debug_hex32(sysref);
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print_debug("\n\r");
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//gliu = get_memory_speed();
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get_memory_speed();
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//print_debug("Target Memory Clock ");
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//print_debug_hex32(gliu);
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//print_debug("\n\r");
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msr.hi = 0x00000019;
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msr.lo = 0x06de0378;
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wrmsr(0x4c000014, msr);
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msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
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wrmsr(0x4c000014, msr);
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print_debug("Reset PLL\n\r");
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msr.lo |= ((1<<14) |(1<<13) | (1<<0));
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wrmsr(0x4c000014,msr);
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print_debug("should not be here\n\r");
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}
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